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AS5SS128K36 Datasheet(PDF) 11 Page - Austin Semiconductor |
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AS5SS128K36 Datasheet(HTML) 11 Page - Austin Semiconductor |
11 / 16 page SRAM AS5SS128K36 Austin Semiconductor, Inc. AS5SS128K36 Rev. 2.0 12/00 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 AC TEST CONDITIONS OUTPUT LOADS Fig. 2 OUTPUT LOAD EQUIVALENT Fig. 1 OUTPUT LOAD EQUIVALENT Input pulse levels Input timing reference levels Input slew rate Output reference levels Output load Vss to 3.3V 1.5V 1 ns 1.5V See Figures 1 and 2 3.3v Q 351 Ω 5 pF 317 Ω Q 50 Ω Z 0=50Ω V T =1.5V LOAD DERATING CURVES The ASI 128K x 36 ZBL SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. |
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