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AS8F128K32

Austin Semiconductor, Inc.

AS8F128K32

Rev. 2.0 5/03

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

7

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which in

turn invokes the Embedded Erase algorithm. The device does

not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any

controls or timings during these operations. The Command

Definitions table shows the address and data requirements for

the chip erase command sequence.

Any commands written to the chip during the Embedded

Erase algorithm are ignored.

The system can determine the status of the erase

operation by using I/O7 or I/O6. See “Write Operation Status”

for information on these status bits. When the Embedded Erase

algorithm is complete, the device returns to reading array data

and addresses are no longer latched.

Figure 2 illustrates the algorithm for the erase operation.

See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to the Chip/Sector Erase

Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the address of the sector to be

erased, and the sector erase command. The Command Defini-

tions table shows the address and data requirements for the

sector erase command sequence.

The device does not require the system to preprogram the

memory prior to erase. The Embedded Erase algorithm

automatically programs and verifies the sector for an all zero

data pattern prior to electrical erase. The system is not required

to provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-

out of 50 ms begins. During the time-out period, additional

sector addresses and sector erase commands may be written.

Loading the sector erase buffer may be done in any sequence,

and the number of sectors may be from one sector to all sectors.

The time between these additional cycles must be less than

50 ms, otherwise the last address and command might not be

accepted, and erasure may begin. It is recommended that

processor interrupts be disabled during this time to ensure all

commands are accepted. The interrupts can be re-enabled after

the last Sector Erase command is written. If the time between

additional sector erase commands can be assumed to be less

than 50 ms, the system need not monitor I/O3*. Any command

during the time-out period resets the device to reading array

data. The system must rewrite the command sequence and any

additional sector addresses and commands.

The system can monitor I/O3* to determine if the sector

erase timer has timed out. (See the “I/O3*: Sector Erase Timer”

section.) The time-out begins from the rising edge of the final

WE# pulse in the command sequence.

Once the sector erase operation has begun, all other

commands are ignored.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are no longer

latched. The system can determine the status of the erase

operation by using I/O7 or I/O6. Refer to “Write Operation

Status” for information on these status bits.

Figure 2 illustrates the algorithm for the erase operation.

Refer to the Erase/Program Operations tables in the “AC

Characteristics” section for parameters, and to the Sector Erase

Operations Timing diagram for timing waveforms.

FIGURE 1: Program Operation

command sequence.