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AS8S128K32 Datasheet(PDF) 5 Page - Austin Semiconductor |
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AS8S128K32 Datasheet(HTML) 5 Page - Austin Semiconductor |
5 / 12 page SRAM SRAM SRAM SRAM SRAM AS8S128K32 Austin Semiconductor, Inc. AS8S128K32 Rev. 4.0 5/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 7. At any given temperature and voltage condition, t HZCE, is less than tLZCE, and tHZWE is less than tLZWE. 8. ?W/E is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enable are held in their active state. 10. Address valid prior to or coincident with latest occurring chip enable. 11. t RC= READ cycle time. 12. Chip enable (?C/E) and write enable (?W/E) can initiate and terminate a WRITE cycle. 13. 32 bit operation NOTES 1. All voltages referenced to V SS (GND). 2. -3v for pulse width <20ns. 3. ICC is dependent on output loading and cycle rates. The specified value applies with the outputs 4. This parameter is sampled. 5. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 6. t HZCE, tHZOE and tHZWE are specified with CL= 5pF as in Fig. 2. Transition is measured +/- 200 mV typical from steady state coltage, allowing for actual tester RC time constant. open, and f= HZ. tRC(MIN) 1 LOW V CC DATA RETENTION WAVEFORM tR tCDR DATA RETENTION MODE DATA RETENTION MODE VDR VDR Vcc CE\ 4.5V 4.5V >2V V IH V IL DATA RETENTION ELECTRICAL CHARACTERISTICS DESCRIPTION SYMBOL MIN MAX UNITS NOTES VCC for Retention Data VDR 2-- V CE\ > VCC - 0.2V VCC = 2.0V ICCDR -- 6 mA VIN > VCC - 0.2V VCC = 3V ICCDR -- 11.6 mA Chip Deselect to Data Retention Time tCDR 0-- ns 4 Operation Recovery Time tR tRC ns 4, 11 Data Retention Current CONDITIONS |
Similar Part No. - AS8S128K32_03 |
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Similar Description - AS8S128K32_03 |
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