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1389CS–CASIC–06-Nov-06

ATC18 Summary

Table 7-3 gives the range of permitted via programmable ROM configurations.

Notes:

1. CM = 16, 32, 64: Column Mux option

2. Min = 256 for CM = 16; min = 512 for CM = 32; min = 1K for CM = 64

7.4

Two-port Synchronous Register File

Key features of the two-port synchronous register file are:

• 2-Port (1R, 1W) high-speed/low-power Register File

• 500MHz worst-case cycle time for 32 words x 32 bits

• Zero Quiescent Current

• 3-state outputs

• Several aspect ratios for optimization

• Separate Data-in, Data-out pins

• Optional sub word write decode

The two-port synchronous register file compiler is a 2-port (1R, 1W) memory designed in 0.18-

micron process. This is a high-speed/low-power synchronous register file compiler. The quies-

cent current consumption is zero when all Register File inputs (including CLKA and CLKB) are

stable. The compiler is optimized for a power supply voltage range of 1.6V to 2.0V and can oper-

ate at voltages as low as 1.2V. The Register File instances can be built with several aspect

ratios for maximum area and performance optimization. Separate clocks (CLKA, CLKB), output

(QB), and input (DA) pins allow independent read and write cycles. Built-in BIST interface allows

for easy connection to most memBIST solutions. The memory also includes a sub-word feature

where selective write to each group of 2-, 4- or 8-bit sub-words can be done. A maskable write

enable signal is optionally provided for each 2-, 4-, or 8-bit group. Within limits, the user has flex-

ibility in specifying the logical size of the Register File, including word size, number of address

locations and column mux.

Table 7-4 gives the range of permitted two-port synchronous register file configurations.

Notes:

1. CM = 1, 2, 4: Column Mux option

2. Minimum word size is 8 at column mux 4.

Table 7-3.

Configuration Range

Parameter

Min

Max

Increment

Address Locations (words)

64K

Word Size (Number of I/O bits)

8

64

1 bit

Total Bits in Core (Word Size x Address Locations)

2K

1M

Table 7-4.

Configuration Range

Parameter

Min

Max

Increment

Address Locations (words)

8

1024

Word Size (Number of I/O bits)

256

1 bit

Total Bits in Core (Word Size x Address Locations)

16

16K