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HI-8588CRT-10 Datasheet(PDF) 2 Page - Holt Integrated Circuits |
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HI-8588CRT-10 Datasheet(HTML) 2 Page - Holt Integrated Circuits |
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2 / 6 page  TEST HI-8588-10 FUNCTIONAL DESCRIPTION TXBOUT TXAOUT TX1IN TX0IN ARINC Channel RINB RINA TESTA TESTB { HARDWIRE OR DRIVE FROM LOGIC ROUTB ROUTA 5V VCC V- -15V GND TXD0 TXD1 RXD0 RXD1 HI-6010 8 BIT BUS ARINC Channel 1 2 8 6 7 4 3 4 5 6 7 2 3 HI-8588-10 APPLICATION INFORMATION 15V V+ 8 5 HI-8586 SLP1.5 1 RECEIVER Figure 1 shows the general architecture of the ARINC 429 receiver. The receiver operates off the VCC supply only. The inputs RINA and RINB each require 35K of resis- tance of which 25K is internal to the chip. The series re- sistance is connected to level translators whose resistance to Ground is typically 10K . In order for the voltage trans- lation not to be adversely affected, an external 10K series resister must be added to each ARINC input. The HI-8588-10 device is typically chosen for applications where external series resistors are required in its lightning protection circuitry. After level translation, the inputs are buffered and become inputs to a differential amplifier. The amplitude of the differ- ential signal is compared to levels derived from a divider W W W W Figure 2 shows a possible application of the HI-8588-10 interfacing an ARINC receive channel to the HI-6010 which in turn inter- faces to an 8-bit bus. RINA RINB NULL ZERO NULL ONE TESTA ROUTB ROUTA FIGURE 1 - RECEIVER BLOCK DIAGRAM SQ R LATCH ESD PROTECTION AND TRANSLATION 10KW 10KW between VCC and Ground. The nominal settings corre- spond to a One/Zero amplitude of 6.0V and a Null ampli- tude of 3.3V. The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of the TESTA and TESTB pins. Unlike the HI-8588, if TESTA and TESTB are both One, the HI-8588-10 outputs are pulled low in- stead of being tri-stated. This allows the digital outputs of a transmitter to be connected to the test inputs through control logic for self-test purposes. GND LATCH SQ TESTB R TESTA TESTB TEST FIGURE 2 - APPLICATION DIAGRAM HOLT INTEGRATED CIRCUITS 2 |
Similar Part No. - HI-8588CRT-10 |
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Similar Description - HI-8588CRT-10 |
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