HI-8683, HI-8684

HOLT INTEGRATED CIRCUITS

4

ERROR CHECKING

READING RECEIVE BUFFER

Once a word gap is detected, the data word in the input reg-

ister is transferred to the receive buffer and checked for er-

rors.

When parity detection is enabled (PARITY ENB high), the

received word is checked for odd parity. If there is a parity

error, the 32nd bit of the received data word is set high.

If parity checking is disabled (PARITY ENB low) the 32nd

bit of the data word is always the 32nd ARINC bit received.

The ERROR flag output is set high upon receipt of a word

gap and the number of bits received since the previous

word gap is less than or greater than 32. The ERROR flag

is reset low when the next valid ARINC word is written into

the receive buffer or when

is pulsed low.

When the data word is transferred to the receive buffer, the

DATA RDY pin goes high. The data word can then be read

in four 8-bit bytes by pulsing the

input low as indi-

cated in Figure 5. The first read cycle resets DATA RDY

low and increments an internal counter to the next 8-bit

byte. The counter continues to increment on each read cy-

cle until all four bytes are read. The relationship between

each bit of an ARINC word received and each bit of the four

8-bit data bus bytes is specified in Figure 2.

When a new ARINC word is received it always overwrites

the receive buffer. If the first byte of the previous word has

not been read, then previous data is lost and the receive

buffer will contain the new ARINC word. However, if the

DATA RDY pin goes high between the reading of the first

and fourth bytes, the previous read bytes are no longer

valid because the unread bytes have been overwritten by

the new ARINC word. Also, the next read will be of the first

byte of the new ARINC word since the internal byte counter

is always reset to the first byte when new data is trans-

ferred to the receive buffer.

RESET

READ

FUNCTIONAL DESCRIPTION (cont.)

TRUTH TABLE 1.

RINA

RINB

TESTA

TESTB

RXA

RXB

-1.50 to +1.50V

-1.50V to +1.50V

0

0

0

0

-3.25V to -6.50V

+3.25V to +6.50V

0

0

0

1

+3.25V to +6.50V

-3.25V to -6.50V

0

0

1

0

X

X

0

101

X

X

1

010

X

X

1

100

X = don't care

Read

Byte

Data Bus Bits

ARINC Bits

1st

Byte 1

D0 - D7

ARINC 1 - ARINC 8

2nd

Byte 2

D0 - D7

ARINC 9 - ARINC 16

3rd

Byte 3

D0 - D7

ARINC 17 - ARINC 24

4th

Byte 4

D0 - D7

ARINC 25 - ARINC 32

FIGURE 2. ORDER OF RECEIVED DATA

RESET

TEST MODE (HI-8684 only)

A low on the

input sets a flip-flop which initializes

the internal logic. When

goes high, the internal

logic remains in the initialized state until the first word gap is

detected preventing reception of a partial word.

The built-in differential line receiver on the HI-8684 can be

disabled allowing the data and clock detection circuitry to

be driven directly with digital signals. The logical OR func-

tion of the TESTA and TESTB is defined in Truth Table 1.

The two inputs can be used for testing the receiver logic and

for inputting ARINC 429 type data derived from another

source / protocol. See Figure 4 for typical test input timing.

The device should always be initialized with

imme-

diately after entering the test mode to clear a partial word

that may have been received since the last word gap. Oth-

erwise, an ERROR condition may occur and the first 32

bits of data on the test inputs may not be properly re-

ceived.

Also, when entering the test mode, both TESTA and

TESTB should be set high and held in that state for at

least one word gap period (17 gap clocks) after

goes high.

When exiting the test mode, both test inputs should be held

low and the device initialized with

RESET

RESET

RESET

RESET

RESET.