HI-8588

FUNCTIONAL DESCRIPTION

RINA

RINB

NULL

ZERO

NULL

ONE

TEST

TESTA

TEST

TEST

TESTB

TESTA ' TESTB

ROUTB

TESTA ' TESTB

ROUTA

FIGURE 1 - RECEIVER BLOCK DIAGRAM

TEST

R

SQ

R

LATCH

SQ

LATCH

ESD

PROTECTION

AND

TRANSLATION

TXBOUT

TXAOUT

TX0IN

TX1IN

ARINC

Channel

RINB

RINA

TESTA

TESTB

{

HARDWIRE

OR

DRIVE FROM LOGIC

ROUTB

ROUTA

5V

VCC

V-

-15V

GND

TXD1

TXD0

RXD0

RXD1

HI-6010

8 BIT BUS

ARINC

Channel

1

2

8

6

7

4

3

4

5

6

7

3

2

HI-8588

FIGURE 2 - APPLICATION DIAGRAM

APPLICATION INFORMATION

15V

V+

8

5

HI-8586

SLP1.5

1

RECEIVER

Figure 1 shows the general architecture of the ARINC 429

receiver. The receiver operates off the VCC supply only.

The inputs RINA and RINB each have series resistors, typi-

cally 35K ohms. They connect to level translators whose

resistance to Ground is typically 10K ohms. Therefore, any

series resistance added to the inputs will affect the voltage

translation.

After level translation, the inputs are buffered and become

inputs to a differential amplifier. The amplitude of the differ-

ential signal is compared to levels derived from a divider be-

tween VCC and Ground. The nominal settings correspond

to a One/Zero amplitude of 6.0V and a Null amplitude of

3.3V.

The status of the ARINC receiver input is latched. A

Null input resets the latches and a One or Zero input

sets the latches.

The logic at the output is controlled by the test signal

which is generated by the logical OR of the TESTA and

TESTB pins. If TESTA and TESTB are both One, then

the receiver is powered down and the output pins float.

The powerdown does not disconnect the internal resis-

tors at the ARINC input.

Figure 2 shows a possible application

of the HI-8588 interfacing an ARINC re-

ceive channel to the HI-6010 which in

turn interfaces to an 8-bit bus.

HOLT INTEGRATED CIRCUITS

2