RECEIVER LOGIC OPERATION

BIT TIMING

BIT RATE

PULSE RISE TIME

PULSE FALL TIME

PULSE WIDTH

Figure 2 shows a block diagram of the logic section of each receiver.

The ARINC 429 specification contains the following timing specifi-

cation for the received data:

100K BPS ± 1% 12K -14.5K BPS

1.5 ± 0.5 µsec

10 ± 5 µsec

1.5 ± 0.5 µsec

10 ± 5 µsec

5 µsec ± 5%

34.5 to 41.7 µsec

The HI-8581 and HI-8589 accept signals that meet these specifica-

tions and rejects outside the tolerances. The way the logic opera-

tion achieves this is described below:

1. Key to the performance of the timing checking logic is an ac-

curate 1MHz clock source. Less than 0.1% error is recom-

mended.

2. The sampling shift registers are 10 bits long and must show

three consecutive Ones, Zeros or Nulls to be considered valid

data. Additionally, for data bits, the One or Zero in the upper

bits of the sampling shift registers must be followed by a Null in

the lower bits within the data bit time.

For a Null in the word

gap, three consecutive Nulls must be found in both the upper

and lower bits of the sampling shift register. In this manner the

minimum pulse width is guaranteed.

HIGH SPEED

LOW SPEED

FUNCTIONAL DESCRIPTION (cont.)

3. Each data bit must follow its predecessor by not less than

8 samples and no more than 12 samples. In this manner the

bit rate is checked. With exactly 1MHz input clock frequency,

the acceptable data bit rates are as follows:

83K BPS

10.4K BPS

125K BPS

15.6K BPS

4. The Word Gap timer samples the Null shift register every

10 input clocks (80 for low speed) after the last data bit of a

valid reception. If the Null is present, the Word Gap counter

is incremented. A count of 3 will enable the next reception.

The receiver parity circuit counts Ones received, including the par-

ity bit, ARINC bit 32. If the result is odd, then "0" will appear in the

32nd bit.

HIGH SPEED

LOW SPEED

DATA BIT RATE MIN

DATA BIT RATE MAX

RECEIVER PARITY

RETRIEVING DATA

Once 32 valid bits are recognized, the receiver logic generates

an End of Sequence (EOS). If the receiver decoder is enabled

and the 9th and 10th ARINC bits match the control word pro-

gram bits or if the receiver decoder is disabled, then EOS clocks

the data ready flag flip flop to a "1",

or

(or both) will go

low. The data flag for a receiver will remain low until after

ARINC bytes from that receiver are retrieved. This is accom-

plished by first activating

with SEL, the byte selector, low to

retrieve the first byte and then activating

with SEL high to re-

trieve the second byte.

retrieves data from receiver 1 and

retrieves data from receiver 2.

If another ARINC word is received and a new EOS occurs before

the two bytes are retrieved, the data is overwritten by the new

word.

D/R1

D/R2

EN

EN

EN1

EN2

both

SEL

EN

D/R

DECODER

CONTROL

BITS

/

MUX

CONTROL

LATCH

ENABLE

CONTROL

32 TO 16 DRIVER

32 BIT LATCH

32 BIT SHIFT REGISTER

TO PINS

CONTROL

BIT BD14

CLOCK

OPTION

CLOCK

CLK

BIT

COUNTER

AND

END OF

SEQUENCE

PARITY

CHECK

32ND

BIT

DATA

BIT CLOCK

EOS

WORD GAP

WORD GAP

TIMER

BIT CLOCK

END

START

SEQUENCE

CONTROL

ERROR

CLOCK

ERROR

DETECTION

SHIFT REGISTER

SHIFT REGISTER

NULL

ZEROS

SHIFT REGISTER

ONES

EOS

BITS9&10

FIGURE 2.

RECEIVER BLOCK DIAGRAM

HI-8581, HI-8589

HOLT INTEGRATED CIRCUITS

4