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BQ27200DRKR Datasheet(PDF) 10 Page - Texas Instruments |
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BQ27200DRKR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 31 page www.ti.com RBI Input GPIO Layout Considerations Gas Gauge Operation bq27000, bq27200 SLUS556D – SEPTEMBER 2004 – REVISED MARCH 2006 FUNCTIONAL DESCRIPTION (continued) The RBI input pin is used with an external capacitor to provide backup potential to the internal registers when VCC drops below V(POR). VCC is output on RBI when VCC is above V(POR), charging the capacitor. An optional 1 M Ω resistor can be added from the RBI pin to V CC. This allows the IC to maintain RAM register data for an indefinite period when the battery voltage is below V(POR) and above 1.3 V. The bqJUNIOR checks for RAM corruption by storing a redundant copy of the high byte of NAC and a checkbyte computed from LMD, CYCL, CYCT, and other critical data. After a reset, the bqJUNIOR compares the redundant NAC and checkbyte values. If the checks are correct, NAC, LMD, CYCL, and CYCT are retained; and the CI bit in FLAGS is left unchanged. If these checks are not correct, NAC, CYCL, and CYCT are cleared; LMD is initialized from EEPROM and the CI bit in FLAGS is set to 1. All other RAM is initialized on all resets. The GPIO pin can be used as an input or an output. The initial state can be established by programming bit 7 in the PKCFG EEPROM location. The input/output state can be changed at any time by changing the value in bit 7 of MODE. The auto-calibrating DSCC approach effectively cancels the internal offset voltage within the bqJUNIOR, but any external offset caused by PCB layout must be programmed in the EEPROM to be cancelled. The magnitude and variability of the external offset makes it critical to pay special attention to the PCB layout. To obtain optimal performance, the decoupling capacitor from VCC to VSS and the filter capacitors from SRP and SRN to VSS should be placed as closely as possible to the bqJUNIOR, with short trace runs to both signal and VSS pins. All low-current VSS connections should be kept separate from the high-current discharge path from the battery and should tie into the high-current trace at a point directly next to the sense resistor. This should be a trace connection to the edge or inside of the sense resistor connection, so that no part of the VSS interconnections carry any load current and no portion of the high-current PCB trace is included in the effective sense resistor (i.e. Kelvin connection). Figure 4 illustrates an operational overview of the gas gauge function. The bqJUNIOR measures the capacity of the battery during actual use conditions and updates the Last Measured Discharge (LMD) register with the latest measured value. The bqJUNIOR retains the learned LMD value unless a full reset occurs. By measuring the capacity that the battery delivers as it is discharged from full to the EDV1 threshold without any disqualifying events, the bqJUNIOR learns the capacity of the battery. The bqJUNIOR does not need to learn a new capacity on each full discharge, and only a discharge during normal use conditions should be used to learn a new capacity. In the event that some abnormal situation occurs that could cause a significant reduction in learned capacity, the LMD value is restricted to a maximum LMD learn-down during any single learning discharge of LMD/8. The Capacity Inaccurate (CI) bit in FLAGS is cleared after a learning cycle. This bit remains cleared unless a full reset occurs or the cycle count since the last learning cycle (CYCL) reaches a count of 32. The full condition is defined as Nominal Available Capacity (NAC) = LMD. The Valid Discharge Flag (VDQ) in the FLAGS register is set when this condition occurs and remains set until the learning discharge cycle completes or an event occurs that disqualifies the learning cycle. The learning discharge cycle completes when the battery is discharged to the condition where VOLT ≤ EDV1 threshold. The EDV1 threshold should be set at a voltage that ensures at least 6.25% of battery capacity below that threshold. The EDVF threshold should be set at a voltage that the system sees as the zero-capacity battery voltage. The bqJUNIOR EDV detection is designed to prevent premature detection of the EDV thresholds due to dynamic load variations. EDV detection has a dynamically adjusted delay of up to 21.5 s with RSOC ≥ 6% and down to 3 s when RSOC = 0%. The bqJUNIOR does not learn the capacity between EDV1 and EDVF thresholds, but assumes that the capacity is 6.25% of LMD; so, care should be taken to set EDV1 based on the characteristics of the battery. The measured LMD value is determined by measuring the capacity delivered from the battery from NAC = LMD until VOLT = EDV1, plus LMD/16 to account for the 6.25% capacity remaining below the EDV1 threshold. 10 Submit Documentation Feedback |
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