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LTC6079 Datasheet(PDF) 9 Page - Linear Technology |
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LTC6079 Datasheet(HTML) 9 Page - Linear Technology |
9 / 20 page LTC6078/LTC6079 9 60789fa Figure 1. Op Amp with Input Voltage Clamp Preserving Input Precision Preserving input accuracy of the LTC6078/LTC6079 re- quires that the application circuit and PC board layout do not introduce errors comparable or greater than the 10µV typical offset of the amplifiers. Temperature differentials across the input connections can generate thermocouple voltages of 10’s of microvolts so the connections to the input leads should be short, close together and away from heat dissipating components. Air current across the board can also generate temperature differentials. The extremely low input bias currents (0.2pA typical) al- low high accuracy to be maintained with high impedance sources and feedback resistors. Leakage currents on the PC board can be higher than the input bias current. For example, 10GΩ of leakage between a 5V supply lead and an input lead will generate 500pA! Surround the input leads with a guard ring driven to the same potential as the input common mode to avoid excessive leakage in high impedance applications. Input Clamps Large differential voltages across the inputs over very long time periods can impact the precisely trimmed input offset voltage of the LTC6078/LTC6079. As an example, a 2V differential voltage between the inputs over a period of 100 hours can shift the input offset voltage by tens of microvolts. If the amplifier is to be subjected to large differential input voltages, adding back-to-back diodes between the two inputs will minimize this shift and retain the DC precision. If necessary, current-limiting series resistors can be added in front of the diodes, as shown in Figure 1. These diodes are not necessary for normal closed loop applications. – + 500 Ω 500 Ω 60789 F01 APPLICATIO S I FOR ATIO Capacitive Load LTC6078/LTC6079 can drive capactive load up to 200pF in unity gain. The capacitive load driving capability increases as the amplifier is used in higher gain configurations. A small series resistance between the ouput and the load further increases the amount of capacitance the amplifier can drive. ⎯S⎯H⎯D⎯N Pins Pins 5 and 6 are used for power shutdown on the LTC6078 in the DD package. If they are floating, internal current sources pull Pins 5 and 6 to V+ and the amplifiers operate normally. In shutdown, the amplifier output is high imped- ance, and each amplifier draws less than 2µA current. When the chip is turned on, the supply current per amplifier is about 35µA larger than its normal values for 50µs. Rail-to-Rail Input The input stage of LTC6078/LTC6079 combines both PMOS and NMOS differential pairs, extending its input common mode voltage range to both positive and negative supply voltages. At high input common mode range, the NMOS pair is on. At low common mode range, the PMOS pair is on. The transition happens when the common voltage is between 1.3V and 0.9V below the positive supply. Thermal Hysteresis Figure 2 shows the input offset hysteresis of LTC6078MS8 for 3 thermal cycles from –45°C to 90°C. The typical offset shift after the 3 cycles is only 1µV. Figure 2. VOS Thermal Hysteresis of LTC6078MS8 VOS CHANGE FROM INITIAL VALUE 50 45 40 35 30 25 20 15 10 5 0 60789 F02 –5 5 –3 –4 –2 –1 2 4 6 01 3 VS = 3V VCM = 0.5V 1ST CYCLE 2ND CYCLE 3RD CYCLE |
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Similar Description - LTC6079 |
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