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PCF8558U Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCF8558U Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 24 page 1998 Apr 07 5 Philips Semiconductors Objective specification Universal LCD driver for small graphic panels PCF8558 FUNCTIONAL DESCRIPTION LCD bias voltage generator The intermediate bias voltages for the LCD display are generated and buffered on-chip. This removes the need for an external resistor bias chain and significantly reduces the system power consumption. Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD. External clock If an external clock is to be used it is input at the OSC pin. The resulting display frame frequency is given by . Only in the power-down state is the clock allowed to be stopped (OSC connected to VSS), otherwise the LCD will be frozen in a state where a DC voltage is applied to it. Power-on reset The on-chip power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 2 oscillator cycles to execute. These oscillator cycles must be provided from the external clock source if the internal oscillator is not used. If this is not done, the device may not respond to command sequences transmitted via the I2C-bus interface. Power-down The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no internal power-on reset, no bias level generation and all LCD outputs are internally connected to VDD) when PD = logic 1. During power-down the information in the RAMs and the internal chip states are preserved. Instruction execution during power-down is possible if an externally clock signal is applied to pad OSC. Registers The PCF8558 has one 8-bit register, time shared as a Command Register (CR) and a Data Register (DR). The command register stores the command code such as display on or display off and address information for the f frame f OSC 3072 ------------- = Display Data RAM (DDRAM). Both registers can be written to but not read from by the system controller. Address Counter (AC) The address counter assigns addresses to the DDRAM for writing and is set by Y2 to Y0 in the command and X6 to X0 in the address. After a write operation the address counter is automatically incremented by 1 in accordance with the V flag. Display Data RAM (DDRAM) The PCF8558 contains a 40 × 101-bit static RAM which stores the display data. The RAM is divided into 5 banks of 101 bytes (5 × 8 × 101 bits). During RAM access, data is transferred to the RAM via the I2C-bus. There is a direct correspondence between the X address and the column output number. Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. Display control The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off and normal/inverse video) is set by bits E and D in the command word. LCD row and column drivers The PCF8558 contains 40 row and 101 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 3 illustrates typical waveforms. Unused outputs should be left unconnected. The bias voltage levels, V2 to V5, are chosen to give optimum display contrast for a multiplex rate of 1 : 40. Table 1 Voltage bias levels LEVEL VOLTAGE V2 0.8635 × (V DD − VLCD) V3 0.7270 × (VDD − VLCD) V4 0.2730 × (V DD − VLCD) V5 0.1365 × (V DD − VLCD) |
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