4

4901A–RKE–11/05

ATA3745

3.

RF Front End

The RF front end of the receiver is a heterodyne configuration that converts the input signal into

a 1-MHz IF signal. As shown in the block diagram, the front end consists of an LNA (low noise

amplifier), LO (local oscillator), a mixer and an RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal

oscillator) generates the reference frequency f

erates the drive voltage frequency f

is divided by a factor of 64. The divided frequency is compared to f

detector. The current output of the phase frequency detector is connected to a passive loop filter

and thereby generates the control voltage V

is controlled such that f

the following formula:

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. Fig-

ure 3-1shows the proper layout, with the crystal connected to GND via a capacitor CL. The value

of that capacitor is recommended by the crystal supplier. The value of CL should be optimized

for the individual board layout to achieve the exact value of f

designing the system in terms of receiving bandwidth, the accuracy of the crystal and XTO must

be considered.

Figure 3-1.

PLL Peripherals

The passive loop filter connected to pin LF is designed for a loop bandwidth of B

This value for B

the appropriate loop filter components to achieve the desired loop bandwidth. If the filter compo-

nents are changed for any reason, please note that the maximum capacitive load at pin LF is

limited. If the capacitive load is exceeded, a bit check may no longer be possible since f

not settle in time before the bit check starts to evaluate the incoming data stream. Therefore, self

polling also does not work in that case.

f

mula:

f

XTO

f

LO

64

--------

=

DVCC

XTO

LF

LFVCC

LFGND

C

L

C10

R1

C9

V

S

R1 = 820

Ω

C9 = 4.7 nF

C10 = 1 nF

V

S

f

LO

f

RF

f

IF

–

=