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AT24HC02B Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT24HC02B Datasheet(HTML) 10 Page - ATMEL Corporation |
10 / 16 page 10 AT24HC02B [Preliminary] 5192A–SEEPR–1/07 Once the device address with the read/write select bit set to “1” is clocked in and acknowl- edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 11 on page 11). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a follow- ing stop condition (see Figure 11 on page 11). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran- dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con- tinue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 13 on page 12). Figure 8. Device Address Figure 9. Byte Write MSB |
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