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ATMEGA325P Datasheet(PDF) 47 Page - ATMEL Corporation |
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ATMEGA325P Datasheet(HTML) 47 Page - ATMEL Corporation |
47 / 336 page 47 8023A–AVR–12/06 ATmega325P/3250P Figure 9-1. Reset Logic 9.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characterizations” on page 309. The POR is activated when- ever V CC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V CC rise. The RESET signal is activated again, without any delay, when V CC decreases below the detection level. Figure 9-2. MCU Start-up, RESET Tied to V CC MCU Status Register (MCUSR) Brown-out Reset Circuit BODLEVEL [1..0] Delay Counters CKSEL[3:0] CK TIMEOUT DATA BUS Clock Generator SPIKE FILTER Pull-up Resistor JTAG Reset Register Watchdog Oscillator SUT[1:0] Power-on Reset Circuit V RESET TIME-OUT INTERNAL RESET t TOUT V POT V RST CC |
Similar Part No. - ATMEGA325P_06 |
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Similar Description - ATMEGA325P_06 |
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