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ATMEGA325P Datasheet(PDF) 60 Page - ATMEL Corporation |
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ATMEGA325P Datasheet(HTML) 60 Page - ATMEL Corporation |
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60 / 336 page  60 8023A–AVR–12/06 ATmega325P/3250P 11.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 11-1. Figure 11-1. Pin Change Interrupt 11.3 Register Description 11.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre- sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 11-1. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF PCINT(0) pin_sync pcint_syn pin_lat D Q LE pcint_setflag PCIF clk clk PCINT(0) in PCMSK(x) pcint_in_(0) 0 x Bit 7 6 543210 (0x69) – – – – – – ISC01 ISC00 EICRA Read/Write RRRRRR R/W R/W Initial Value 0 0 000000 |
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