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PCK2002DL Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCK2002DL Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 12 page Philips Semiconductors Product data PCK2002 0–300 MHz I2C 1:18 clock buffer 2001 Jul 19 9 AC WAVEFORMS VM = 1.5 V VX = VOL + 0.3 V VY = VOH –0.3 V VOL and VOH are the typical output voltage drop that occur with the output load. BUF_IN INPUT VM tPLH tPHL BUF_OUT VM VM VM SW00246 VDD Figure 1. Load circuitry for switching times. tPLZ tPZL VI nOE INPUT GND VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL VOH OUTPUT HIGH-to-OFF OFF-to-HIGH VSS outputs enabled outputs enabled outputs disabled tPHZ VM VM VM tPZH VX VY SW00245 VDD Figure 2. 3-State enable and disable times DUTY CYCLE TSDKP TSDKH TSDRISE TSDFALL TSDKL 2.4 1.5 0.4 SW00247 Figure 3. Buffer Output clock TEST CIRCUIT PULSE GENERATOR RT VI D.U.T. VO CL VDD TEST S1 tPLH/tPHL Open tPLZ/tPZL 2 <VDD tPHZ/tPZH VSS Open VSS S1 2 <VDD 500 Ω 500 Ω SW00251 Figure 4. Load circuitry for switching times |
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