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NLAS3158MNR2G Datasheet(PDF) 1 Page - ON Semiconductor

Part # NLAS3158MNR2G
Description  Low Voltage Dual SPDT Analog Switch Dual 2:1 Multiplexer
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 1
1
Publication Order Number:
NLAS3158/D
NLAS3158
Low Voltage Dual SPDT
Analog Switch Dual 2:1
Multiplexer
The NLAS3158 is an advanced CMOS analog switch fabricated
with silicon gate CMOS technology. It achieves very low
propagation delay and RDSON resistances while maintaining CMOS
low power dissipation. Analog and digital voltages that may vary
across the full power−supply range (from VCC to GND). This device
is a drop in replacement for the PI5A3158.
The select pin has overvoltage protection that allows voltages
above VCC, up to 7.0 V to be present on the pin without damage or
di srupt i o n of ope r a t i o n of the pa rt , re ga rdl e ss of the
operating voltage.
Features
High Speed: tPD = 1.0 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C
Standard CMOS Logic Levels
High Bandwidth, Improved Linearity
Low RDSON: 8 W Max at 3 V
Break Before Make Circuitry, Prevents Inadvertent Shorts
This is a Pb−Free Device
Typical Applications
Switches Standard NTSC/PAL Video, Audio, SPDIF and HDTV
May be used for Clock Switching, Data MUX’ing, etc.
Can Switch Balanced Signal Pairs, e.g. LVDS u 200 Mb/s
Important Information
Latchup Performance Exceeds 300 mA
Pin for Pin Drop in for PI5A3158
TDFN Package, 3x1 mm
ESD Performance: Human Body Model; u 2000 V;
Machine Model;
u 200 V
Extended Automotive Temperature Range −55°C to +125°C
(See Appendix A)
DFN12
MN SUFFIX
CASE 485AG
http://onsemi.com
MARKING DIAGRAM
AS = Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
L
H
FUNCTION TABLE
Select Input
Function
B0 Connected to A
B1 Connected to A
1
12
1
ASM
G
G
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
Figure 1. Pinout (Top View)
S1
A0
GND
A1
0B0
1
2
3
12
10
VCC
11
4
5
6
9
7
8
1B0
GND
1B1
VCC
S0
0B1


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