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PCK2509SADH Datasheet(PDF) 3 Page - NXP Semiconductors |
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PCK2509SADH Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 10 page Philips Semiconductors Product specification PCK2509SA 50–150 MHz 1:9 SDRAM clock driver 2000 Dec 01 3 PIN DESCRIPTIONS PIN NUMBER SYMBOL TYPE NAME, FUNCTION, and DIRECTION 1 AGND GND Analog ground. AGND provides the ground reference for the analog circuitry. 2, 10, 15, 22 VCC PWR Power supply 3, 4, 5, 8, 9 1Y (0–4) OUT Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0–4) is enabled via the1G input. These outputs can be disabled to a logic LOW state by de-asserting the 1G control input. Each output has an integrated 25 Ω series-damping resistor. 6, 7, 18, 19 GND GND Ground 11 1G IN Output bank enable. 1G is the output enable for outputs 1Y(0–4). When 1G is LOW, outputs 1Y(0–4) are disabled to a logic LOW state. When 1G is HIGH, all outputs 1Y(0–4) are enabled and switch at the same frequency as CLK. 12 FBOUT OUT Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25 Ω series-damping resistor. 13 FBIN IN Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 14 2G IN Output bank enable. 2G is the output enable for outputs 2Y(0–3). When 2G is LOW, outputs 2Y(0–3) are disabled to a logic LOW state. When 2G is HIGH, all outputs 2Y(0–3) are enabled and switch at the same frequency as CLK. 16, 17, 20, 21 2Y (0–3) OUT Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0–3) is enabled via the 2G input. These outputs can be disabled to a logic LOW state by de-asserting the 2G control input. Each output has an integrated 25 Ω series-damping resistor. 23 AVCC PWR Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. 24 CLK IN Clock input. CLK provides the clock signal to be distributed by the PCK2509SA clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FUNCTION TABLE INPUTS OUTPUTS 1G 2G CLK 1Y (0–4) 2Y (0–3) FBOUT X X L L L L L L H L L H L H H L H H H L H H L H H H H H H H |
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