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BUF16820AIDAPRG4 Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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BUF16820AIDAPRG4 Datasheet(HTML) 5 Page - Burr-Brown (TI) |
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5 / 30 page  BUF16820 SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006 www.ti.com 5 APPLICATIONS INFORMATION The BUF16820 programmable voltage reference allows fast and easy adjustment of 14 programmable reference outputs and two channels for VCOM adjustment, each with 10-bit resolution. It allows very simple, time-efficient adjustment of the gamma reference and VCOM voltages. The BUF16820 is programmed through a high-speed, standard, two-wire interface. The BUF16820 features a double-register structure for each DAC channel to simplify the implementation of dynamic gamma control. This structure allows pre-loading of register data and rapid updating of all channels simultaneously. Buffers 1−9 are able to swing to within 200mV of the positive supply rail, and to within 0.6V of the negative supply rail. Buffers 10−14 are able to swing to within 0.8V of the positive supply rail and to within 200mV of the negative supply rail. The BUF16820 can be powered using an analog supply voltage from 8.5V to 18V, and a digital supply from 2V to 5.5V. The digital supply must be applied prior to, or simultaneously with, the analog supply to avoid excessive current and power consumption; damage to the device may occur if it is left connected only to the analog supply for extended periods of time. Figure 7 shows the power supply timing requirements. V SD GND D V S GND Digital Supply: Analog Supply: t 1: 0s minimum delay between Digital Supply and Analog Supply. t 1 Figure 7. Power Supply Timing Requirements Figure 8 shows the BUF16820 in a typical configuration. In this configuration, the BUF16820 device address is 74h. The output of each digital-to-analog converter (DAC) is immediately updated as soon as data are received in the corresponding register (LD = 0). For maximum dynamic range, set VREFH = VS − 0.2V, and VREFL = GND + 0.2V. TWO-WIRE BUS OVERVIEW The BUF16820 communicates through an industry- standard, two-wire interface to receive data in slave mode. This standard uses a two-wire, open-drain interface that supports multiple devices on a single bus. Bus lines are driven to a logic low level only. The device that initiates the communication is called a master, and the devices controlled by the master are slaves.The master generates the serial clock on the clock signal line (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, the master initiates a START condition by pulling the data signal line (SDA) from a HIGH to a LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the 9th clock pulse, the slave being addressed responds to the master by generating an acknowledge and pulling SDA LOW. Data transfer is then initiated and eight bits of data are sent followed by an acknowledge bit. During data transfer, SDA must remain stable while SCL is HIGH. Any change in SDA while SCL is HIGH will be interpreted as a START or STOP condition. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH while SCL is HIGH. The BUF16820 can act only as a slave device; therefore, it never drives SCL. The SCL pin is only an input for the BUF16820. Table 1 and Table 2 summarize the address and command codes, respectively, for the BUF16820. Table 1. Quick-Reference Table of Addresses DEVICE/COMPONENT ADDRESS BUF16820 Address: A0 pin is LOW (device will acknowledge on address 74h) 1110100 A0 pin is HIGH (device will acknowledge on address 75h) 1110101 Table 2. Command Codes Quick-Reference COMMAND CODE General Call Reset Address byte of 00h followed by a data byte of 06h. High-Speed Mode 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This byte is called the Hs master code. ADDRESSING THE BUF16820 The address of the BUF16820 is 111010x, where x is the state of the A0 pin. When the A0 pin is LOW, the device will acknowledge on address 74h (1110100). If the A0 pin is HIGH, the device will acknowledge on address 75h (1110101). Other valid addresses are possible through a simple mask change. Contact your TI representative for information. |
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