1

Rev. B

10/23/06

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

IS61C256AL

FEATURES

• High-speed access time: 10, 12 ns

• CMOS Low Power Operation

— 1 mW (typical) CMOS standby

— 125 mW (typical) operating

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single 5V power supply

• Lead-free available

DESCRIPTION

The

32,768 word by 8-bit static RAMs. It is fabricated using

reliable process coupled with innovative circuit design

techniques, yields access times as fast as 10 ns maximum.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down to 150 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active

LOW Chip Enable (

CE) input and an active LOW Output

Enable (

OE) input. The active LOW Write Enable (WE)

controls both writing and reading of the memory.

The IS61C256AL is pin compatible with other 32Kx8 SRAMs

and are available in 28-pin SOJ and TSOP (Type I)

packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A14

CE

OE

WE

32K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7

32K x 8 HIGH-SPEED CMOS STATIC RAM

OCTOBER 2006