Multiple-Output Clock Generators with

Dual PLLs and OTP

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11

Applications Information

Crystal Selection

When using a crystal with the MAX9471/MAX9472s’

internal oscillator, connect the crystal to X1 and X2.

Choose an AT-cut crystal that oscillates on its funda-

mental mode with ±30ppm and loading capacitance

less than 14pF. To achieve a wide VCXO tuning range,

select a crystal with motional capacitance greater than

7fF and connect 6pF or less shunt capacitors at X1 and

X2 to ground. When the VCXO is used as an oscillator,

select both shunt capacitors to be approximately 13pF.

The optimal shunt capacitors for achieving minimum

frequency offset can be determined experimentally.

Board Layout Considerations and

Bypassing

The MAX9471/MAX9472s’ oscillator frequencies make

proper layout important to ensure stability. For best per-

formance, place components as close as possible to

the device.

Digital or AC transient signals on GND can create noise

at the clock output. Return GND to the highest quality

0.1µF capacitor, placed as close as possible to the

device. Careful PC board ground layout minimizes

crosstalk between the outputs and digital inputs.

Chip Information

PROCESS: CMOS

14

13

12

11

10

9

8

1

2

3

4

5

6

7

X2

GND

FS0

FS1

X1

TOP VIEW

GND

CLK3

CLK2

CLK1

GND

TUNE

MAX9472

TSSOP

PD

+

Pin Configurations (continued)