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SCANSTA112SM Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # SCANSTA112SM
Description  7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

SCANSTA112SM Datasheet(HTML) 6 Page - National Semiconductor (TI)

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TABLE 1. Pin Descriptions
Pin Name
Description
No.
Pins
I/O
VCC
10
N/A
Power
GND
10
N/A
Ground
RESET
1
I
RESET Input: will force a reset of the device regardless of the current state.
ADDMASK
1
I
ADDRESS MASK input: Allows masking of lower slot input pins.
MPsel
B1/B0
1
I
MASTER PORT SELECTION: Controls selection of LSP
B0 or LSPB1 as the backplane port.
The unselected port becomes LSP
00. A value of "0" will select LSPB0 as the master port.
SB/S
1
I
Selects ScanBridge or Stitcher Mode.
LSPsel
(0-6)
7
I
In Stitcher Mode these inputs define which LSP’s are to be included in the scan chain
TRANS
1
I
Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit
of the control register at power-up. This value is used to control the presence of registers
and pad-bits in the scan chain while in the stitcher mode.
TLR_TRST
1
I
Sets the driven value of TRST
0-5 when LSP TAPs are in TLR and the device is not being
reset. During RESET = "0" or TRST
B = "0" (IgnoreReset = "0") TRSTn = "0". This pin is to be
tied low to match the function of the SCANSTA111
TLR_TRST
6
1
I
This pin affects TRST of LSP
6 only. This pin is to be tied low to match the function of the
SCANSTA111
TDI
B0, TDIB1
2
I
BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA112
through this input pin. MPsel
B1/B0 determines which port is the master backplane port and
which is LSP
00. This input has a 25K
Ω internal pull-up resistor and no ESD clamp diode
(ESD is controlled with an alternate method). When the device is power-off (V
DD floating),
this input appears to be a capacitive load to ground (Note 1). When V
DD = 0V (i.e.; not
floating but tied to V
SS) this input appears to be a capacitive load with the pull-up to ground.
TMS
B0, TMSB1
2
I/O
BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
’STA112. Also controls sequencing of the TAPs which are on the local scan chains.
MPsel
B1/B0 determines which port is the master backplane port and which is LSP00. This
bidirectional TRI-STATE pin has 24mA of drive current, with a 25K
Ω internal pull-up resistor
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is
power-off (V
DD floating), this input appears to be a capacitive load to ground (Note 1). When
V
DD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the
pull-up to ground.
TDO
B0, TDOB1
2
I/O
BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA112 and the
local TAPs, back toward the scan master controller. This bidirectional TRI-STATE pin has
12mA of drive current. MPsel
B1/B0 determines which port is the master backplane port and
which is LSP
00. Output is sampled during interrogation addressing. When the device is
power-off (V
DD = 0V or floating), this output appears to be a capacitive load (Note 1).
TCK
B0, TCKB1
2
I/O
TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls
all scan operations of the ’STA112 and of the local scan ports. MPsel
B1/B0 determines which
port is the master backplane port and which is LSP
00. These bidirectional TRI-STATE pins
have 24mA of drive current with hysterisis. This input has no pull-up resistor and no ESD
clamp diode (ESD is controlled with an alternate method). When the device is power-off (V
DD
floating), this input appears to be a capacitive load to ground (Note 1). When V
DD = 0V (i.e.;
not floating but tied to V
SS) this input appears to be a capacitive load to ground.
TRST
B0, TRSTB1
2
I/O
TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA112 logic.
MPsel
B1/B0 determines which port is the master backplane port and which is LSP00. This
bidirectional TRI-STATE pin has 24mA of drive current, with a 25K
Ω internal pull-up resistor
and no ESD clamp diode (ESD is controlled with an alternate method). When the device is
power-off (V
DD floating), this pin appears to be a capacitive load to ground (Note 1). When
V
DD = 0V (i.e.; not floating but tied to VSS) this input appears to be a capacitive load with the
pull-up to ground.
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