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MC68HC908GT8 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC68HC908GT8 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 292 page  Revision History MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 4 Freescale Semiconductor The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet 1 of 2) Date Revision Level Description Page Number(s) March, 2002 N/A Original release N/A May, 2002 1.0 7.2 Features — Corrected third bulleted item to reflect ±4 percent variability 77 Figure 15-1. Forced Monitor Mode (Low) — Reworked for clarity 211 Figure 15-2. Forced Monitor Mode (High) — Reworked for clarity 211 Figure 15-3. Standard Monitor Mode — Reworked for clarity 212 Table 15-1. Monitor Mode Signal Requirements and Options — Reworked for clarity 214 Figure 12-4. Port A I/O Circuit — Reworked to correct pullup resistor 143 Figure 12-11. Port C I/O Circuit — Reworked to correct pullup resistor 148 Figure 12-15. Port D I/O Circuit — Reworked to correct pullup resistor 151 June, 2002 2.0 Figure 2-2. Control, Status, and Data Registers — Corrected ESCI arbiter data register (SCIADAT) to reflect read-only status 50 Figure 14-19. ESCI Arbiter Control Register (SCIACTL) — Corrected address location designator from $0018 to $000A 170 Figure 14-20. ESCI Arbiter Data Register (SCIADAT) — Corrected address location designator from $0019 to $000B 171 September, 2004 3.0 (Continued on next page) Reformatted to meet current publications standards Throughout 1.5.6 ADC Reference Pins (VREFH and VREFL) — Corrected connections 27 2.6.3 Flash Page Erase Operation — Updated procedure 41 2.6.4 Flash Mass Erase Operation — Updated procedure 42 2.6.5 Flash Program/Read Operation — Updated procedure 43 2.6.6 Flash Block Protection — Description updated for clarity 45 3.3.5 Conversion — Updated for clarity 52 3.6.3 ADC Voltage Reference High Pin (VREFH) — Corrected connections 53 3.6.4 ADC Voltage Reference Low Pin (VREFL) — Corrected connections 53 3.7.1 ADC Status and Control Register — Updated description of the COCO bit 54 Chapter 4 Configuration Register (CONFIG) — Updated COP tmeout selections 57, 59 Chapter 4 Configuration Register (CONFIG) — Updted SSREC bit usage 60 Chapter 5 Computer Operating Properly (COP) Module — Updated timeout selections 62 Figure 5-1. COP Block Diagram — Updated illustration for clarity 61 Table 6-1. Instruction Set Summary — Updated definitions for STOP and WAIT 70 Figure 7-9. Code Example for Switching Clock Sources — Replaced example code 89 Figure 7-10. Code Example for Enabling the Clock Monitor — Replaced example code 90 Figure 14-18. ESCI Prescaler Register (SCPSC) — Corrected address location 172 |
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