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3D3324D-1000 Datasheet(PDF) 1 Page - Data Delay Devices, Inc. |
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3D3324D-1000 Datasheet(HTML) 1 Page - Data Delay Devices, Inc. |
1 / 4 page 3D3324 MONOLITHIC QUADRUPLE FIXED DELAY LINE (SERIES 3D3324) FEATURES • All-silicon, low-power CMOS technology • Vapor phase, IR and wave solderable • Auto-insertable (DIP pkg.) • Low ground bounce noise • Leading- and trailing-edge accuracy • Delay range: 10 through 6000ns • Delay tolerance: 2% or 1.0ns • Temperature stability: ±3% typ (-40C to 85C) • Vdd stability: ±1% typical (3.0V to 3.6V) • Minimum input pulse width: 20% of total delay • 14-pin Gull-Wing available as drop-in replacement for hybrid delay lines FUNCTIONAL DESCRIPTION The 3D3324 Quadruple Delay Line product family consists of fixed- delay CMOS integrated circuits. Each package contains four matched, independent delay lines. Delay values can range from 10ns through 6000ns. The input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. The 3D3324 is CMOS-compatible and features both rising- and falling-edge accuracy. The all-CMOS 3D3324 integrated circuit has been designed as a reliable, economic alternative to hybrid fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 14-pin SOIC. PACKAGES 14 13 12 11 10 9 8 1 2 3 4 5 6 7 I1 N/C I2 I3 I4 N/C GND VDD N/C O1 N/C O2 O3 O4 3D3324-xx DIP 3D3324G-xx Gull-Wing 1 2 3 4 5 6 7 14 13 12 11 10 9 8 I1 N/C I2 I3 I4 N/C GND VDD N/C O1 N/C O2 O3 O4 3D3324D-xx SOIC (150 Mil) PIN DESCRIPTIONS I1 Delay Line 1 Input I2 Delay Line 2 Input I3 Delay Line 3 Input I4 Delay Line 4 Input O1 Delay Line 1 Output O2 Delay Line 2 Output O3 Delay Line 3 Output O4 Delay Line 4 Output VDD +3.3 Volts GND Ground N/C No Connection For mechanical dimensions, click here. For package marking details, click here. TABLE 1: PART NUMBER SPECIFICATIONS PART NUMBER DELAY INPUT RESTRICTIONS DIP-14 3D3324 DIP-14 3D3324G SOIC-14 3D3324D PER LINE (ns) Max Operating Frequency Absolute Max Oper. Freq. Min Operating Pulse Width Absolute Min Oper. P.W. -10 -10 -10 10 ± 1.0 33.3 MHz 100.0 MHz 15.0 ns 5.0 ns -15 -15 -15 15 ± 1.0 22.2 MHz 100.0 MHz 22.5 ns 5.0 ns -20 -20 -20 20 ± 1.0 16.7 MHz 100.0 MHz 30.0 ns 5.0 ns -25 -25 -25 25 ± 1.0 13.3 MHz 83.3 MHz 37.5 ns 6.0 ns -30 -30 -30 30 ± 1.0 11.1 MHz 71.4 MHz 45.0 ns 7.0 ns -40 -40 -40 40 ± 1.0 8.33 MHz 62.5 MHz 60.0 ns 8.0 ns -50 -50 -50 50 ± 1.0 6.67 MHz 50.0 MHz 75.0 ns 10.0 ns -100 -100 -100 100 ± 2.0 3.33 MHz 25.0 MHz 150.0 ns 20.0 ns -200 -200 -200 200 ± 4.0 1.67 MHz 12.5 MHz 300.0 ns 40.0 ns -500 -500 -500 -500 500 ± 10.0 0.67 MHz 5.00 MHz 750.0 ns -1000 -1000 -1000 -1000 1000 ± 20 0.33 MHz 2.50 MHz 1500.0 ns -6000 -6000 -6000 -6000 6000 ±120 0.05 MHz 0.42 MHz 9000.0 ns NOTES: Any delay between 10 and 6000 ns not shown is also available. 2006 Data Delay Devices Doc #06018 DATA DELAY DEVICES, INC. 1 5/10/2006 3 Mt. Prospect Ave. Clifton, NJ 07013 |
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