3D7424D-4 datasheet(3/6 Pages) DATADELAY

Part #	3D7424D-4

Description	MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE

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Manufacturer	DATADELAY [Data Delay Devices, Inc.]

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3D7424

APPLICATION NOTES (CONT’D)

DELAY ACCURACY

There are a number of ways of characterizing the

delay accuracy of a programmable line. The first

is the differential nonlinearity (DNL), also referred

to as the increment error. It is defined as the

deviation of the delay step at a given address

from its nominal value. For all dash numbers, the

DNL is within 1/4 LSB at every address (see

Table 1: Delay Step).

The integrated nonlinearity (INL) is determined

by first constructing the least-squares best fit

straight line through the delay-versus-address

data. The INL is then the deviation of a given

delay from this line. For all dash numbers, the

INL is within 1.0 LSB at every address.

The relative error is defined as follows:

erel = (Ti – T0) – i * Tinc

where i is the address, Ti is the measured delay

at the i’th address, T0 is the measured inherent

delay, and Tinc is the nominal increment. It is very

similar to the INL, but simpler to calculate. For

most dash numbers, the relative error is less than

1/8 LSB at every address (see Table 1: Relative

Tolerance).

The absolute error is defined as follows:

eabs = Ti – (Tinh + i * Tinc)

where Tinh is the nominal inherent delay. The

absolute error tolerance is given for addresses 0

and 15 (see Table 1: Inherent Delay, Total Delay,

respectively). At any intermediate address, the

tolerance can be found via linear interpolation of

the address 0 & address 15 tolerances.

The matching error is a measure of how well the

delay of the four lines track each other when they

are all programmed to the same address. The

lines are typically matched to within 1% or 1ns,

whichever is greater, for all addresses and all

dash numbers.

DELAY STABILITY

The delay of CMOS integrated circuits is strongly

dependent on power supply and temperature.

The 3D7424 utilizes novel compensation circuitry

to minimize the delay variations induced by

fluctuations in power supply and/or temperature.

With regard to stability, the delay of the 3D7424

at a given address, i, can be split into two

components: the inherent delay (T0) and the

relative delay (Ti – T0). These components exhibit

very different stability coefficients, both of which

must be considered in very critical applications.

The thermal coefficient of the relative delay is

limited to

±250 PPM/C, which is equivalent to a

variation, over the -40C to 85C operating range,

of

±1.5% from the room-temperature delay

settings. This holds for dash numbers greater

than 1. For smaller dash numbers, the thermal

drift will be larger and will always be positive. The

thermal coefficient of the inherent delay is

nominally +15ps/C for all dash numbers.

The power supply sensitivity of the relative delay

is

±0.5% over the 4.75V to 5.25V operating

range, with respect to the delay settings at the

nominal 5.0V power supply. This holds for all

dash numbers greater than 1. For smaller dash

numbers, the voltage sensitivity will be greater

and will always be negative. The sensitivity of the

inherent delay is nominally -1ps/mV for all dash

numbers.

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3D7424

Figure 3: Cascading Multiple Devices

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Doc #06019

DATA DELAY DEVICES, INC.

3

6/5/2006

3 Mt. Prospect Ave. Clifton, NJ 07013

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