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3D3522Z-50 Datasheet(PDF) 1 Page - Data Delay Devices, Inc.

Part # 3D3522Z-50
Description  MONOLITHIC MANCHESTER DECODER
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Manufacturer  DATADELAY [Data Delay Devices, Inc.]
Direct Link  http://www.datadelay.com
Logo DATADELAY - Data Delay Devices, Inc.

3D3522Z-50 Datasheet(HTML) 1 Page - Data Delay Devices, Inc.

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3D3522
MONOLITHIC MANCHESTER
DECODER
(SERIES 3D3522)
data
delay
devices, inc.
3
FEATURES
PACKAGES
8
7
6
5
1
2
3
4
RX
CLK
N/C
GND
VDD
N/C
N/C
DATB
3D3522M-xxx DIP (.300)
3D3522H-xxx Gull Wing (.300)
3D3522Z-xxx SOIC (.150)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
RX
N/C
N/C
CLK
N/C
N/C
GND
VDD
N/C
N/C
N/C
N/C
N/C
DATB
3D3522-xxx
DIP (.300)
3D3522G-xxx Gull Wing (.300)
3D3522D-xxx SOIC (.150)
All-silicon, low-power CMOS
technology
3.3V operation
CMOS compatible inputs and
outputs
Vapor phase, IR and wave
solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Maximum data rate: 50 MBaud
Data rate range:
±15%
For mechanical dimensions, click
here.
For package marking details, click
here.
FUNCTIONAL DESCRIPTION
The 3D3522 product family consists of monolithic CMOS Manchester
Decoders. The unit accepts at the RX input a bi-phase-level,
embedded-clock signal. In this encoding mode, a logic one is
represented by a high-to-low transition within the bit cell, while a logic
zero is represented by a low-to-high transition. The recovered clock
and data signals are presented on CLK and DATB, respectively, with
the data signal inverted. The operating baud rate (in MBaud) is specified by the dash number. The input
baud rate may vary by as much as
±15% from the nominal device baud rate without compromising the
integrity of the information received.
Because the 3D3522 is not PLL-based, it does not require a long preamble in order to lock onto the
received signal. Rather, the device requires at most one bit cell before the data presented at the output is
valid. This is extremely useful in cases where the information arrives in bursts and the input is otherwise
turned off.
The all-CMOS 3D3522 integrated circuit has been designed as a reliable, economic alternative to hybrid
Manchester Decoders. It is CMOS-compatible and is offered in standard 8-pin and 14-pin auto-insertable
DIPs and space saving surface mount 8-pin and 14-pin SOICs.
TABLE 1: PART NUMBER SPECIFICATIONS
PIN DESCRIPTIONS
RX
Signal Input
CLK
Signal Output (Clock)
DATB Signal Output (Data)
VDD
+3.3 Volts
GND
Ground
PART
BAUD RATE (MBaud)
NUMBER
Nominal
Minimum
Maximum
3D3522-0.5
0.50
0.43
0.57
3D3522-1
1.00
0.85
1.15
3D3522-5
5.00
4.25
5.75
3D3522-10
10.00
8.50
11.50
3D3522-20
20.00
17.00
23.00
3D3522-25
25.00
21.25
28.75
3D3522-50
50.00
42.50
57.50
NOTES: Any baud rate between 0.5 and 50 MBaud not shown is also available at no extra cost.
2006 Data Delay Devices
Doc #06005
DATA DELAY DEVICES, INC.
1
5/8/2006
3 Mt. Prospect Ave. Clifton, NJ 07013


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