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MR4A08ACYS35 Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MR4A08ACYS35 Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
11 / 20 page Timing Specifications MR0A16A Advanced Information Data Sheet, Rev. 0 Freescale Semiconductor 11 Table 11. Write Cycle Timing 2 (E Controlled)1, 2, 3, 4, 5 Parameter Symbol Min Max Unit Write cycle time6 tAVAV 35 — ns Address set-up time tAVEL 0— ns Address valid to end of write (G high) tAVEH 18 — ns Address valid to end of write (G low) tAVEH 20 — ns Enable to end of write (G high) tELEH tELWH 15 — ns Enable to end of write (G low)7, 8 tELEH tELWH 15 — ns Data valid to end of write tDVEH 10 — ns Data hold time tEHDX 0— ns Write recovery time tEHAX 12 — ns NOTES: 1 A write occurs during the overlap of E low and W low. 2 Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. 3 If G goes low at the same time or after W goes low, the output will remain in a high-impedance state. 4 After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. 5 The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 6 All write cycle timings are referenced from the last valid address to the first transition address. 7 If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. 8 If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. |
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