Timing Specifications

MR0A16A Advanced Information Data Sheet, Rev. 0

Freescale Semiconductor

11

Parameter

Symbol

Min

Max

Unit

35

—

ns

Address set-up time

0—

ns

Address valid to end of write (G high)

18

—

ns

Address valid to end of write (G low)

20

—

ns

Enable to end of write (G high)

15

—

ns

15

—

ns

Data valid to end of write

10

—

ns

Data hold time

0—

ns

Write recovery time

12

—

ns

NOTES:

1

A write occurs during the overlap of E low and W low.

2

Due to product sensitivities to noise, power supplies must be properly grounded and decoupled

and bus contention conditions must be minimized or eliminated during read and write cycles.

3

If G goes low at the same time or after W goes low, the output will remain in a high-impedance

state.

4

After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a

minimum of 2 ns.

5

The minimum time between E being asserted low in one cycle to E being asserted low in a

subsequent cycle is the same as the minimum cycle time allowed for the device.

6

All write cycle timings are referenced from the last valid address to the first transition address.

7

If E goes low at the same time or after W goes low, the output will remain in a high-impedance

state.

8

If E goes high at the same time or before W goes high, the output will remain in a high-impedance

state.