UCC2817A, UCC2818A

UCC3817A, UCC3818A

SLUS577B − SEPTEMBER, 2003 − REVISED FEBRUARY 2006

6

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PIN ASSIGNMENTS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CAI

4

I

Current amplifier noninverting input

CAOUT

3

O

Current amplifier output

CT

14

I

Oscillator timing capacitor

DRVOUT

16

O

Gate drive

GND

1

−

Ground

IAC

6

I

Current proportional to input voltage

MOUT

5

I/O

Multiplier output and current amplifier inverting input

OVP/EN

10

I

Over-voltage/enable

PKLMT

2

I

PFC peak current limit

RT

12

I

Oscillator charging current

SS

13

I

Soft-start

VAOUT

7

O

Voltage amplifier output

VCC

15

I

Positive supply voltage

VFF

8

I

Feed-forward voltage

VSENSE

11

I

Voltage amplifier inverting input

VREF

9

O

Voltage reference output

Pin Descriptions

CAI: Place a resistor between this pin and the GND side of current sense resistor. This input and the inverting

input (MOUT) remain functional down to and below GND.

CAOUT: This is the output of a wide bandwidth operational amplifier that senses line current and commands

the PFC pulse-width modulator (PWM) to force the correct duty cycle. Compensation components are placed

between CAOUT and MOUT.

CT: A capacitor from CT to GND sets the PWM oscillator frequency according to:

f

[

0.6

RT

CT

The lead from the oscillator timing capacitor to GND should be as short and direct as possible.

DRVOUT: The output drive for the boost switch is a totem-pole MOSFET gate driver on DRVOUT. To avoid the

excessive overshoot of the DRVOUT while driving a capacitive load, a series gate current-limiting/damping

resistor is recommended to prevent interaction between the gate impedance and the output driver. The value

gate resistance of resistance 11

Ω would be required for a maximum VCC voltage of 18 V and for 1.2 A of

typical).

R

VCC

* I

MAX

R

pulldown

I

MAX

GND: All voltages measured with respect to ground. VCC and REF should be bypassed directly to GND with

a 0.1-

µF or larger ceramic capacitor.