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ADATE207BBPZ Datasheet(PDF) 10 Page - Analog Devices |
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ADATE207BBPZ Datasheet(HTML) 10 Page - Analog Devices |
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10 / 36 page  ADATE207 Rev. 0 | Page 10 of 36 Pin No. Mnemonic Input/Output1 Type Description H2 COMP_L_CH1_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the low comparator differential inputs of Channel 1. M20 COMP_L_CH2_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the low comparator differential Inputs of Channel 2. H19 COMP_L_CH3_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the low comparator differential inputs of Channel 3. M4 COMP_H_CH0_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the high comparator differential inputs of Channel 0. H3 COMP_H_CH1_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the high comparator differential inputs of Channel 1. M17 COMP_H_CH2_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the high comparator differential inputs of Channel 2. H18 COMP_H_CH3_T A, I, O Analog Center Tap. Center tap of two 50 Ω resistor terminations for the high comparator differential inputs of Channel 3. W15, V15, Y16, W16, Y17, W17, U16, V17, U18, T17, U19, U20, T19, T20, R18, R19 CS_AD[15:0] I, O LVCMOS25 Bidirectional Multiplexed Address/Data Bus for CSR Register Access. Clocked by MCLK. U13 CS_AS I LVCMOS25 Address Strobe for the Address/Data Bus. Clocked by MCLK. V14 CS_RW_B I LVCMOS25 Read/Write Bar Signal for the Address Data Bus. High for reads. Clocked by MCLK. Y15 CLKGEN_MD_EN I LVCMOS25 Mode Pin for Clock Generation. Tie to Logic low for normal operation. L1 MCLK_P D, I LVCMOS25 Positive Portion of the Master Clock Signal. K2 MCLK_N D, I LVCMOS25 Negative Portion of the Master Clock Signal. R4 RESET_B I LVCMOS25 Reset Bar. Active low power-on reset signal. D19 TDI I LVCMOS25 Scan Chain Data In. Tie to Logic high for normal operation. C8 TDO O LVCMOS25 Scan Chain Data Out. A7 TCK I LVCMOS25 Scan Chain Clock. Tie to Logic high for normal operation. D18 TMS I LVCMOS25 Scan Chain Mode. Tie to Logic high for normal operation. E17 TRST_B I LVCMOS25 Active Low Scan Chain Reset. Tie to Logic low for normal operation. R1 REF_1K A, I, O Analog Controls the output current of the differential open drain outputs. P3 T_DIODE A, I, O Analog Thermal Sensing Diode Anode. Force current and measure voltage to measure die temperature stability. T2 TESTMODE I LVCMOS25 Must be connected to VSS. F2, F1, F19, F20, T1, R3, R2, R20, N4, N17, P18 NC No Connect. Must be left unconnected. SHIELD A, I, O, P GND Connect to VSS. R17, U15, D9, D11, D12, D13, U10, U9, V7, V5 IOVSS P GND Power, 0.0 V. U8, U6, T18, V16 IOVDD P VDD Power, 2.5 V. C9, C11, C13, C15, V11, V9 IOVDD P Power, 2.5 V. A3 to A1 VSS P Power, 0.0 V |
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