ADG1404YRUZ datasheet(9/17 Pages) AD

Part #	ADG1404YRUZ

Description	2??Max On Resistance, 짹15 V/12 V/짹5 V 4:1 iCMOS??Multiplexer

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Manufacturer	AD [Analog Devices]

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Preliminary Technical Data

ADG1404

Rev. PrB | Page 9 of 17

TERMINOLOGY

IDD

The positive supply current.

ISS

The negative supply current.

VD (VS)

The analog voltage on Terminals D and S.

RON

The ohmic resistance between D and S.

RFLAT(ON)

Flatness is defined as the difference between the maximum and

minimum value of on resistance, as measured over the specified

analog signal range.

IS (Off)

The source leakage current with the switch off.

ID (Off)

The drain leakage current with the switch off.

ID, IS (On)

The channel leakage current with the switch on.

VINL

The maximum input voltage for Logic 0.

VINH

The minimum input voltage for Logic 1.

IINL (IINH)

The input current of the digital input.

CS (Off)

The off switch source capacitance, which is measured with

reference to ground.

CD (Off)

The off switch drain capacitance, which is measured with

reference to ground.

CD, CS (On)

The on switch capacitance, which is measured with reference to

ground.

CIN

The digital input capacitance.

tON (EN)

The delay between applying the digital control input and the

output switching on. See Figure 24, Test Circuit 4.

tOFF (EN)

The delay between applying the digital control input and the

output switching off.

Charge Injection

A measure of the glitch impulse transferred from the digital

input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one

channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to

the fundamental.

tTRANS

The delay time between the 50% and 90% points of the digital

input and switch on condition when switching from one

address state to another.

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