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IA82527-PLC44A-R Datasheet(PDF) 11 Page - InnovASIC, Inc |
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IA82527-PLC44A-R Datasheet(HTML) 11 Page - InnovASIC, Inc |
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11 / 45 page  IA82527 04 May 2007 CAN Serial Communications Controller As of Production Ver. 00 PRELIMINARY Copyright 2007 EN21070504-00 www.Innovasic.com Customer Support: Page 11 of 45 1-888-824-4184 © Table 3. IA82527 Pin/Signal Descriptions, continued Pin Signal Name PLCC QFP Description as ale/as 5 43 address strobe. Input. Active High. Mode 2. When the IA82527 is configured to operate in either the 8-bit multiplexed non-Intel ® architecture mode (Mode 2), this signal latches the address into the device during the address phase of the bus cycle. NOTE: If the IA82527 is configured to operate in Mode 3 (8-bit non- multiplexed non-Intel ® architecture), this pin must be tied high. clkout — 27 21 clock out. Output (push-pull). This output provides a programmable clock frequency. The frequency is set via the Clockout Register (1FH) and can range from the frequency of the xtal (crystal) input to xtal/n, where n can be an integer value from 2 through 15. This output allows the IA82527 to clock other devices such as the host CPU. cp a1/ad1/cp 3 41 clock phase. Input. Serial Interface Mode. When this input is a logic 0, data are sampled on the rising edge of sclk. When this input is a logic 1, data are sampled on the falling edge of sclk. cs_n — 8 2 chip select. Input. Active Low (Modes 0–3); Selectable Active Level (Serial Interface Mode). When the IA82527 is configured to operate in one of the parallel interface modes (Modes 0–3) or the Serial Interface Mode, this input, during its active state, selects the device allowing CPU access. For Serial Interface Mode operation, the active state is selectable (i.e., either high or low) via the IA8257 csas pin. csas a2/ad2/csas 2 40 chip select active state. Input. Serial Interface Mode. When this input is a logic 0, the cs_n input is configured to function active low. When this input is a logic 1, the cs_n input is configured to function active high. d0 ad8/d0/p1.0 38 32 d1 ad9/d1/p1.1 37 31 d2 ad10/d2/p1.2 36 30 d3 ad11/d3/p1.3 35 29 d4 ad12/d4/p1.4 34 28 d5 ad13/d5/p1.5 33 27 d6 ad14/d6/p1.6 32 26 d7 ad15/d7/p1.7 31 25 data bits 7–0. Input/Output. Mode 3. When the IA82527 is configured to operate in the 8-bit non- multiplexed non-Intel ® architecture mode (Mode 3), these lines provide the 8-bit data bus to the device. continued . . . |
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