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PHD24N03 Datasheet(PDF) 1 Page - NXP Semiconductors |
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PHD24N03 Datasheet(HTML) 1 Page - NXP Semiconductors |
1 / 8 page Philips Semiconductors Preliminary specification TrenchMOS transistor PHD24N03LT Logic level FET FEATURES SYMBOL QUICK REFERENCE DATA • ’Trench’ technology V DSS = 30 V • Very low on-state resistance • Fast switching I D = 24 A • Stable off-state characteristics • High thermal cycling performance R DS(ON) ≤ 56 mΩ (VGS = 5 V) • Low thermal resistance R DS(ON) ≤ 50 mΩ (VGS = 10 V) GENERAL DESCRIPTION PINNING SOT428 (DPAK) N-channel enhancement mode, PIN DESCRIPTION logic level, field-effect power transistor in a plastic envelope 1 gate using ’trench’ technology. The device has very low on-state 2 drain 1 resistance. It is intended for use in dc to dc converters and general 3 source purpose switching applications. tab drain The PHD24N03LT is supplied in the SOT428 (DPAK) surface mounting package. LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DSS Drain-source voltage T j = 25 ˚C to 175˚C - 30 V V DGR Drain-gate voltage T j = 25 ˚C to 175˚C; RGS = 20 kΩ -30 V V GS Gate-source voltage - ± 13 V I D Continuous drain current T mb = 25 ˚C - 24 A T mb = 100 ˚C - 20 A I DM Pulsed drain current T mb = 25 ˚C - 96 A P D Total power dissipation T mb = 25 ˚C - 60 W T j, Tstg Operating junction and - 55 175 ˚C storage temperature THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction - 2.5 K/W to mounting base R th j-a Thermal resistance junction pcb mounted, minimum footprint 50 - K/W to ambient d g s 1 2 3 tab 1 it is not possible to make connection to pin 2 of the SOT428 package. December 1999 1 Rev 1.100 |
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