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CDCE401YS Datasheet(PDF) 6 Page - Texas Instruments |
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CDCE401YS Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page www.ti.com ENTER REGISTER PROGRAMMING MODE SDATA EN 0 t 2 DATA 0 1 1 0 0 SDATA DELAYED t 1 t 6 t f t 5 t 4 t 8 t r T0042-03 t 3 t 7 CDCE401 SCAS820 – JUNE 2006 Figure 2 shows the timing behavior of data to be written into SDATA. The sequence shown is 00 1100. If the high period is as short as t1, this is interpreted as a 0. If the high period is as long as t3, this is interpreted as a 1. This behavior is achieved by shifting the incoming signal SDATA by time t5 into signal SDATA_DELAYED. As can be seen in Figure 2, SDATA_DELAYED can be used to latch (or strobe) SDATA. The specification for the timings t1 – t8, tr, and tf are given in the Timing Requirements section of this document. Figure 2. Timing Diagram for SDATA Programming 6 Submit Documentation Feedback |
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