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K7I643684M-EI30 Datasheet(PDF) 3 Page - Samsung semiconductor |
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K7I643684M-EI30 Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 18 page 2Mx36 & 4Mx18 DDRII CIO b4 SRAM K7I643684M K7I641884M - 3 - Rev. 1.3 March 2007 2Mx36-bit, 4Mx18-bit DDRII CIO b4 SRAM FEATURES FUNCTIONAL BLOCK DIAGRAM • 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide output data valid window and future fre- quency scaling. • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O . • Pipelined, double-data rate operation. • Common data input/output bus. • HSTL I/O • Full data coherency, providing most current data. • Synchronous pipeline read with self timed late write. • Registered address, control and data input/output. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 4-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input clocks(K and K) for accurate DDR timing at clock rising edges only. • Two input clocks for output data(C and C) to minimize clock-skew and flight-time mismatches. • Two echo clocks (CQ and CQ) to enhance output data traceability. • Single address bus. • Byte write function. • Simple depth expansion with no data contention. • Programmable output impedance. • JTAG 1149.1 compatible test access port. • 165FBGA(11x15 ball array FBGA) with body size of 15x17mm & Lead Free * -F(E)C(I) F(E) [Package type]: E-Pb Free, F-Pb C(I) [Operating Temperature]: C-Commercial, I-Industrial Org. Part Number Cycle Time Access Time Unit RoHS Avail. X36 K7I643684M-F(E)C(I)30 3.3 0.45 ns √ K7I643684M-F(E)C(I)25 4.0 0.45 ns √ K7I643684M-FC(I)20 5.0 0.45 ns • K7I643684M-FC(I)16 6.0 0.50 ns • X18 K7I641884M-F(E)C(I)30 3.3 0.45 ns √ K7I641884M-F(E)C(I)25 4.0 0.45 ns √ K7I641884M-FC(I)20 5.0 0.45 ns • K7I641884M-FC(I)16 6.0 0.50 ns • LD ADDRESS R/W C C ADD REG & BURST LOGIC DATA REG CLK GEN CTRL LOGIC 2Mx36 (4Mx18) MEMORY ARRAY WRITE DRIVER K K BWX 4(or 2) DQ SELECT OUTPUT CONTROL Notes: 1. Numbers in ( ) are for x18 device. 19 19 (or 20) 36 (or 18) 36 (or 18) 72 72 (Echo Clock out) CQ, CQ 36 (or 18) A0,A1 DDRII SRAM and Double Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology. (or 20) (or 36) (or 36) |
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