Philips Semiconductors

Product specification

N-channel TrenchMOS

™ transistor

PHP11N06LT, PHB11N06LT

Logic level FET

PHD11N06LT

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

V

• Low on-state resistance

• Fast switching

I

• Logic level compatible

R

R

GENERAL DESCRIPTION

N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.

Applications:-

• d.c. to d.c. converters

• switched mode power supplies

The PHP11N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB11N06LT is supplied in the SOT404 (D

The PHD11N06LT is supplied in the SOT428 (DPAK) surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404 (D

SOT428 (DPAK)

PIN

DESCRIPTION

1

gate

2

drain

1

3

source

tab

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DSS

Drain-source voltage

T

-

55

V

V

DGR

Drain-gate voltage

T

-55

V

V

GS

Gate-source voltage

-

± 15

V

V

GSM

Pulsed gate-source voltage

T

-

± 20

V

I

D

Continuous drain current

T

-

10.3

A

T

-

7.3

A

I

DM

Pulsed drain current

T

-

41

A

P

D

Total power dissipation

T

-

33

W

T

Operating junction and

- 55

175

˚C

storage temperature

d

g

s

12 3

tab

13

tab

2

1

2

3

tab

1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.

August 1999

1

Rev 1.000