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DSP56F826BU80E Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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DSP56F826BU80E Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
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8 / 56 page  56F826 Technical Data, Rev. 14 8 Freescale Semiconductor Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Number of Pins Power (VDD, VDDIO or VDDA) (3,4,1) Ground (VSS, VSSIO or VSSA) (3,4,1) PLL and Clock 3 Address Bus1 16 Data Bus1 16 Bus Control 4 Quad Timer Module Ports1 4 JTAG/On-Chip Emulation (OnCE) 6 Dedicated General Purpose Input/Output 16 Synchronous Serial Interface (SSI) Port1 6 Serial Peripheral Interface (SPI) Port1 1. Alternately, GPIO pins 4 Serial Communications Interface (SCI) Ports 4 Interrupt and Program Control 5 |
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