Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHP60N06LT, PHB60N06LT

Logic level FET

FEATURES

SYMBOL

QUICK REFERENCE DATA

• ’Trench’ technology

V

• Very low on-state resistance

• Fast switching

I

• Stable off-state characteristics

• High thermal cycling performance

R

• Low thermal resistance

R

GENERAL DESCRIPTION

N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology.

The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching

applications.

The PHP60N06LT is supplied in the SOT78 (TO220AB) conventional leaded package.

The PHB60N06LT is supplied in the SOT404 surface mounting package.

PINNING

SOT78 (TO220AB)

SOT404

PIN

DESCRIPTION

1

gate

2

drain

1

3

source

tab

drain

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DSS

Drain-source voltage

T

-

55

V

V

DGR

Drain-gate voltage

T

-55

V

V

GS

Gate-source voltage

-

± 13

V

I

D

Continuous drain current

T

-

58

A

T

-

40

A

I

DM

Pulsed drain current

T

-

232

A

P

D

Total power dissipation

T

-

150

W

T

Operating junction and

- 55

175

˚C

storage temperature

d

g

s

13

tab

2

12 3

tab

1 It is not possible to make connection to pin 2 of the SOT404 package.

January 1998

1

Rev 1.300