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MH16V7245BATJ-6 Datasheet(PDF) 7 Page - Mitsubishi Electric Semiconductor |
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MH16V7245BATJ-6 Datasheet(HTML) 7 Page - Mitsubishi Electric Semiconductor |
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7 / 23 page  MITSUBISHI LSIs MH16V7245BATJ -5, -6 Preliminary Spec. MITSUBISHI ELECTRIC 5/Nov./1998 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM MIT-DS-0277-0.0 ( / 23 ) 7 Read and Refresh Cycles Limits Parameter Symbol Unit (Note 22) Write Cycle (Early Write and Delayed Write) (Note 22) Limits Parameter Symbol Unit (Note 24) ns ns ns ns ns ns ns ns ns ns ns ns tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Write cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow Write setup time before /CAS low Write hold time after /CAS iow /RAS hold time after /CAS iow /CAS hold time after /W iow /RAS hold time after W iow Data setup time before /CAS iow or W iow Data hold time after /CAS iow or W iow Write pulse width Note 22: Either tRCH or tRRH must be satisfied for a read cycle. -6 10000 10000 Min Max 10000 10000 10 0 104 60 10 35 20 10 10 -5 15 -6 Min Max tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH tCAL Read cycle time /RAS iow pulse width /CAS iow pulse width /CAS hold time after /RAS iow Read Setup time after /CAS high Read hold time after /CAS iow /RAS hold time after /CAS iow Read hold time after /RAS iow Column address to /RAS hold time /CAS hold time after /OE iow /RAS hold time after /OE iow Column address to /CAS hold time ns ns ns ns ns ns ns ns ns ns ns ns 0 0 104 60 10 43 20 0 35 15 20 Read-Write and Read-Modify-Write Cycles Limits Parameter Symbol Unit (Note23) (Note24) Read write/read modify write cycle time RAS iow pulse width CAS iow pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS iow to W iow Delay time, RAS iow to W iow Delay time, address to W iow OE hold time after W iow tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tOEH ns ns ns ns ns ns ns ns ns ns (Note24) (Note24) Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 24: tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS ≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥tCWD(min), tRWD≥tRWD (min), tAWD≥tAWD(min) and tCPWD ≥tCPWD(min) (for Hyper page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until /CAS or /OE goes back to VIH) is indeteminate. Min Max -6 10000 10000 49 133 44 77 0 32 72 47 15 89 18 15 -5 Min 0 0 84 50 8 30 18 0 30 13 18 13 10000 10000 Max 10000 10000 8 0 84 50 8 30 18 8 8 -5 13 Min Max 13 -5 Min Max -5 10000 10000 43 109 38 65 0 28 60 40 13 75 |
Similar Part No. - MH16V7245BATJ-6 |
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Similar Description - MH16V7245BATJ-6 |
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