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STM704RM6F Datasheet(PDF) 10 Page - STMicroelectronics

Part # STM704RM6F
Description  3V Supervisor with Battery Switchover
Download  32 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM704RM6F Datasheet(HTML) 10 Page - STMicroelectronics

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STM690/704/795/802/804/805/806
10/32
Chip-Enable Gating (STM795 only)
Internal gating of the chip enable (E) signal pre-
vents erroneous data from corrupting the external
CMOS RAM in the event of an undervoltage con-
dition. The STM795 uses a series transmission
gate from E to ECON (see Figure 12). During nor-
mal operation (reset not asserted), the E transmis-
sion gate is enabled and passes all E transitions.
When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting
the CMOS RAM. The short E propagation delay
from E to ECON enables the STM795 to be used
with most µPs. If E is low when reset asserts,
ECON remains low for typically 10µs to permit the
current WRITE cycle to complete.
Chip Enable Input (STM795 only)
The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
VCC passes the reset threshold, the chip-enable
transmission gate disables and E immediately be-
comes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 10µs after reset as-
serts (see Figure 13). This permits the current
WRITE cycle to complete during power-down.
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
first half of the reset time-out period (trec/2). When
the chip enable transmission gate is enabled, the
impedance of E appears as a 40
Ω resistor in se-
ries with the load at ECON. The propagation delay
through the chip-enable transmission gate de-
pends on VCC, the source impedance of the drive
connected to E, and the loading on ECON. The chip
enable propagation delay is production tested
from the 50% point on E to the 50% point on ECON
using a 50
Ω driver and a 50pF load capacitance
(see Figure 36., page 23). For minimum propaga-
tion delay, minimize the capacitive load at ECON
and use a low-output impedance driver.
Chip Enable Output (STM795 only)
When the chip-enable transmission gate is en-
abled, the impedance of ECON is equivalent to a
40
Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects ECON to VOUT (see
Figure 12). This pull-up turns off when the trans-
mission gate is enabled.
Figure 12. Chip-Enable Gating
Figure 13. Chip Enable Waveform (STM795)
AI08802
VRST
VOUT
VCC
COMPARE
ECON
trec
Generator
ECON OUTPUT
CONTROL
RST
E
AI08855c
RST
E
VCC
VRST
VBAT
ECON
trec
trec
½ trec
½ trec
10µs


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