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VM6101 Datasheet(PDF) 6 Page - STMicroelectronics |
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VM6101 Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 17 page Functional description VM6101 6/17 Notes 1. Upon reset, the comparator logic is enabled (EN_HI:EN_LO = 01) with POL_LO = 1 and TH_LO = 0x0008. The INT pin is high when Y channel count > 8. 2. Assuming CONTROL= 0x04, i.e. comparator mode using Y channel count (default value for CONTROL register). 3. Ensure TH_LO < TH_HI otherwise unpredictable results may occur. 2.3 PWM generator The pulse width modulator (PWM) generates a signal which may be used to directly control LCD backlight driver ICs according to ambient light level. There are three registers to control the PWM generator operation: ● PWM_FREQ register bits [4:0] sets the period of the PWM signal. This is adjustable from 12Hz to 400kHz. ● PWM_SENS register bits [4:0] sets the sensitivity of the PWM signal to light level. ● CONTROL register bit 2 = 0 to select PWM output at INT pin. ● CONTROL register bit 3 controls the polarity of the PWM output (default = 0). For more details please refer to Chapter 4: Register description. The curve below shows typical PWM output duty cycle (default polarity) as a function of illumination, with sensitivity setting ranging from 9 to 18, corresponding to typical use cases (10 to 10000 lx illumination). Table 2. Threshold module configurations (TH_CFG register usage) EN_HI: EN_LO INT output INT versus CNT (assumes INT_POL = 0) 00 0 0 01 POL_LO xor (CNT < TH_LO) (POL_LO = 0) 10 POL_HI xor (CNT < TH_HI) (POL_HI = 0) 11 HYST = 0: (POL_LO xor (CNT < TH_LO)) and (POL_HI xor (CNT < TH_HI)) (POL_LO = 1, POL_HI = 0) HYST = 1: see diagram (POL_LO = 1, POL_HI = 0) 0 TH_LO TH_HI 1 0 TH_LO TH_HI 1 0 TH_LO TH_HI 1 0 TH_LO TH_HI 1 |
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