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IA186EM Datasheet(PDF) 7 Page - InnovASIC, Inc |
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IA186EM Datasheet(HTML) 7 Page - InnovASIC, Inc |
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7 / 133 page  IA186EM/IA188EM Data Sheet 8/16-BIT Microcontrollers As of Production Version -03 Bus Interface and Control Bus Interface and Control (BIC) manages all accesses to external memory and external peripherals. These peripherals may be mapped either in memory space or I/O space. The BIC supports both multiplexed and non-multiplexed bus operations. Multiplexed address and data are provided on the ad [15:0] bus, while a non-multiplexed address is provided on the a [19:0] bus. The A bus provides address information for the entire bus cycle (t1-t4), while the ad bus provides address information only during the first (t1) phase of the bus cycle. For more details regarding bus cycles, see the AC waveforms at the end of this datasheet. The IA186EM microcontroller provides two signals that serve as byte write enables: write high byte (whb_n) and write low byte (wlb_n). Obviously, the IA188EM microcontroller requires only a single write byte (wb_n) signal to support its 8-bit data bus. whb_n is the logical OR of the bhe_n and wr_n. wlb_n is the logical OR of ad0 and wr_n. wlb_n is the logical OR of ad0 and wr_n. wb_n is low whenever a byte is written to the IA188EM data bus ad[7:0]. The byte write enables are driven in conjunction with the non-multiplexed address bus a[19:0] to facilitate meeting the timing requirements of common SRAMs. The BIC also provides support for Pseudo-Static RAM (PSRAM) devices. PSRAM is supported in the lower chip select (lcs_n) area only. In order to support PSRAM, the Chip Selects and Control (CSC) must be appropriately programmed. For details regarding this operation, see Chip Selects. Peripheral Control and Registers The on-chip peripherals in the IA186EM/188EM microcontroller are controlled from a 256-byte block of internal registers. Although these registers are actually located in the peripherals they control, they are addressed within a single 256-byte block of I/O spaced and are therefore treated as a functional unit for the purposes of this document. A map of these registers is depicted in Table 1. All write operations performed on the IA188EM should be 8-bit writes, which will still result in 16-bit data transfers to the Peripheral Control Block (PCB) register even if the named register is an 8-bit register. Any read performed to the PCB registers should be word reads. Code written with these points in mind will run correctly on both the IA186EM and IA188EM. However, unpredictable behavior will result in both the IA186EM and IA188EM processors if unaligned read and write accesses are performed. 3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com |
Similar Part No. - IA186EM_04 |
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Similar Description - IA186EM_04 |
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