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LT1374IS8-SYNC Datasheet(PDF) 6 Page - Linear Technology |
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LT1374IS8-SYNC Datasheet(HTML) 6 Page - Linear Technology |
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6 / 32 page  6 LT1374 1374fb FB/SENSE: The feedback pin is the input to the error amplifier which is referenced to an internal 2.42V source. An external resistive divider is used to set the output voltage. The fixed voltage (-5) parts have the divider included on-chip and the FB pin is used as a SENSE pin, connected directly to the 5V output. Three additional functions are performed by the FB pin. When the pin voltage drops below 1.7V, switch current limit is reduced. Below 1.5V the external sync function is disabled. Below 1V, switching frequency is also reduced. See Feedback Pin Function section in Applications Information for details. BOOST: The BOOST pin is used to provide a drive voltage, higher than the input voltage, to the internal bipolar NPN power switch. Without this added voltage, the typical switch voltage loss would be about 1.5V. The additional boost voltage allows the switch to saturate and voltage loss approximates that of a 0.07 Ω FET structure. Effi- ciency improves from 75% for conventional bipolar de- signs to > 89% for these new parts. VIN: This is the collector of the on-chip power NPN switch. This pin powers the internal circuitry and internal regulator when the BIAS pin is not present. At NPN switch on and off, high dI/dt edges occur on this pin. Keep the external bypass and catch diode close to this pin. All trace induc- tance on this path will create a voltage spike at switch off, adding to the VCE voltage across the internal NPN. Both VIN pins of the 16-lead TSSOP package must be shorted together on the PC board. GND: The GND pin connection needs consideration for two reasons. First, it acts as the reference for the regulated output, so load regulation will suffer if the “ground” end of the load is not at the same voltage as the GND pin of the IC. This condition will occur when load current or other currents flow through metal paths between the GND pin and the load ground point. Keep the ground path short between the GND pin and the load and use a ground plane when possible. The second consideration is EMI caused by GND pin current spikes. Internal capacitance between the VSW pin and the GND pin creates very narrow (<10ns) current spikes in the GND pin. If the GND pin is connected to system ground with a long metal trace, this trace may radiate excess EMI. Keep the path between the input bypass and the GND pin short. VSW: The switch pin is the emitter of the on-chip power NPN switch. This pin is driven up to the input pin voltage during switch on time. Inductor current drives the switch pin negative during switch off time. Negative voltage is clamped with the external catch diode. Maximum negative switch voltage allowed is – 0.8V. Both VSW pins of the 16-lead TSSOP package must be shorted together on the PC board. BOOST Pin Current SWITCH CURRENT (A) 0 0 10 20 40 30 60 50 12 3 45 1374 G16 80 70 100 90 DUTY CYCLE = 100% Inductor Core Loss INDUCTANCE ( µH) 05 1.0 0.1 0.01 0.001 10 15 20 20 12 8 4 2 1.2 0.8 0.4 0.2 0.12 0.08 0.04 0.02 25 1374 G01 TYPE 52 POWDERED IRON Kool M µ® PERMALLOY µ = 125 VOUT = 5V, VIN = 10V, IOUT = 1A CORE LOSS IS INDEPENDENT OF LOAD CURRENT UNTIL LOAD CURRENT FALLS LOW ENOUGH FOR CIRCUIT TO GO INTO DISCONTINUOUS MODE VC Pin Shutdown Threshold JUNCTION TEMPERATURE ( °C) –50 1.4 1.2 1.0 0.8 0.6 0.4 100 1374 G11 –25 0 25 50 75 125 SHUTDOWN TYPICAL PERFOR A CE CHARACTERISTICS PI FU CTIO S |
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