Philips Semiconductors

Product specification

PLC18V8Z

Zero standby power

CMOS versatile PAL devices

1997 Aug 08

10

Commercial = 0

Industrial = –40

PLC18V8Z25

(Commercial)

PLC18V8ZIA

(Industrial)

SYMBOL

PARAMETER

FROM

TO

(pF)

MIN

MAX

MIN

MAX

UNIT

Pulse width

Clock period

CLK +

CLK +

200

50

33

33

ns

Clock width High

CLK +

CLK –

200

50

15

15

ns

Clock width Low

CLK –

CLK +

200

50

15

15

ns

Async reset pulse width

I

±, F±

I +, F +

25

25

ns

Hold time

Input or feedback

data hold time

CLK +

Input

±

200

50

0

0

ns

Setup time

Input or feedback

data setup time

I

±, F±

CLK +

200

50

18

18

ns

Propagation delay

Delay from input

to active output

I

±, F±

F

±

200

50

25

25

ns

Clock High to output valid

access Time

CLK +

F

±

200

50

15

15

ns

Product term enable to

outputs off

I

±, F±

F

±

Active-High R = 1.5k

Active-Low R = 550

50

25

25

ns

Product term disable to

outputs off

I

±, F±

F

±

5

25

25

ns

Pin 11 output disable High

to outputs off

OE –

F

±

5

20

20

ns

Pin 11 output enable to

active output

OE +

F

±

Active-High R = 1.5k

Active-Low R = 550

50

20

20

ns

Async reset delay

I

±, F±

F +

30

30

ns

Async reset recovery time

I

±, F±

CLK +

20

20

ns

Sync preset recovery time

I

±, F±

CLK +

20

20

ns

Power-up reset

F +

25

25

ns

Frequency of operation

Maximum frequency

200

50

30

30

MHz

NOTES:

1. Refer also to AC Test Conditions. (Test Load Circuit)

3. Resistor values of 1.5k and 550

Ω provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level.

4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns.