PLHS501I datasheet(10/12 Pages) PHILIPS

Part #	PLHS501I

Description	Programmable macro logic PML

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Manufacturer	PHILIPS [NXP Semiconductors]

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Philips Semiconductors Programmable Logic Devices

Product specification

PLHS501/PLHS501I

Programmable macro logic

PML

™

October 22, 1993

10

MACRO CELL SPECIFICATIONS1 (Continued) (SNAP Resource Summary Designations in Parantheses)

Commercial:Tamb = 0°C to +75°C, 4.75V ≤ VCC ≤ 5.25V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω

Industrial:

Tamb = –40°C to +85°C, 4.5V ≤ VCC ≤ 5.5V, CL = 30pF, R2 = 1000Ω, R1 = 470Ω

AND Output Buffer with 3-State Control

(NOU501)

Tri–Ctrl

In

Out

PARAMETER

LIMITS

SYMBOL

To

(Output)

From

(Input)

MIN

TYP

MAX

UNIT

tPHL

tPLH

Output

In

8.0

11

13

ns

tOE2

tOD2

Out

Tri-Ctrl

8.5

15

12.5

18.5

17.0

ns

Bidirectional and Output Pins: 19, 21, 22, 23, 15 – 18.

NAND Output Buffer

(OUT501)

In

Out

PARAMETER

LIMITS

SYMBOL

To

(Output)

From

(Input)

MIN

TYP

MAX

UNIT

tPHL

tPLH

Out

In

8.5

14

17.5

16.0

ns

Bidirectional Pins: 37 – 40.

Ex–OR Output Buffer

(EXO501)

Out

A

B

Tri–Ctrl

PARAMETER

LIMITS

SYMBOL

To

(Output)

From

(Input)

MIN

TYP

MAX

UNIT

tPHL

tPLH

Out

A or B

8.5

14

17.5

16.0

ns

tOE2

tOD2

Out

Tri-Ctrl

8.5

15

12.5

18.5

17.0

ns

Ex-OR Output Pins: 28 – 33.

NOTES:

1. Limits are guaranteed with internal feedback buffers simultaneously switching cumulative maximum of eight outputs.

2. For 3-State output; output enable times are tested with CL = 30pF to the 1.5V level, and S1 is open for high-impedance to High tests and

closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output

voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed.

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