INPUT

F0 – F7

CE

1.5V

1.5V

1.5V

1.5V

1.5V

tPD

tCE

tCD

VOL

VOH

+3.0V

0V

+3.0V

0V

Read Cycle

Philips Semiconductors Programmable Logic Devices

Product specification

PLS100/PLS101

Programmable logic arrays

(16

× 48 × 8)

October 22, 1993

53

AC ELECTRICAL CHARACTERISTICS

0

LIMITS

SYMBOL

PARAMETER

TO

FROM

MIN

MAX

UNIT

Input

Output

Input

35

50

ns

Output

Chip Enable

15

30

ns

Disable time

Output

Chip Enable

15

30

ns

NOTES:

2. All propagation delays are measured and specified under worst case conditions.

VOLTAGE WAVEFORMS

TEST LOAD CIRCUIT

MEASUREMENTS:

All circuit delays are measured at the +1.5V level of in-

puts and outputs, unless otherwise specified.

90%

10%

5ns

5ns

5ns

5ns

90%

10%

+3.0V

+3.0V

0V

0V

tR

tF

Input Pulses

+5V

CL

R1

R2

S1

GND

F7

F0

INPUTS

I0

I15

CE

OUTPUTS

C2

C1

DUT

NOTE:

C1 and C2 are to bypass VCC to GND.

VCC

TIMING DEFINITIONS

SYMBOL

PARAMETER

Delay between beginning of

Chip Enable Low (with Input

valid) and when Data Output

becomes valid.

Delay between when Chip

Enable becomes High and

Data Output is in off state

(Hi-Z or High).

Delay between beginning of

valid Input (with Chip Enable

Low) and when Data Output

becomes valid.

TIMING DIAGRAM