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PLS159A Datasheet(PDF) 11 Page - NXP Semiconductors |
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PLS159A Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 12 page Philips Semiconductors Programmable Logic Devices Product specification PLS159A Programmable logic sequencer (16 × 45 × 12) October 22, 1993 35 PROGRAM TABLE J/K J/K or D A (controlled) HIGH H LOW L 0 1 2 3 0 1 2 3 4 5 6 7 (OR) Q(N) B(O) POLARITY EA EB F/F MODE 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 T E R M FC C AND I B(I) Q(P) PB RB D3 D2 D1 D0 PIN 5 4 3 2 9 8 7 6 19 18 17 16 15 14 13 12 AND OR CONTROL NOTES 1. The device is shipped with all links intact. Thus a back- ground of entries corresponding to states of virgin links exists in the table, shown BLANK for clarity. 2. Program unused C, I, B, and Q bits in the AND array as (–). Program unused Q, B, P, and R bits in the OR array as (–) or (A), as applicable. 3. Unused Terms can be left blank. 4. Q (P) and Q (N) are respectively the present and next states of flip-flops Q. INACTIVE O I, B, Q H I, B, Q L DON’T CARE – INACTIVE O GENERATE A PROPAGATE TRANSPARENT – I, B(I), Q(P) C ACTIVE A INACTIVE P, R, B(O) (Q = D) TOGGLE O SET H RESET L HOLD – (Q = J/K) IDLE O CONTROL A ENABLE DISABLE – EA, B (POL) F/F MODE LA RA PA LB |
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