MBM29SL800TE-10PW datasheet(2/52 Pages) SPANSION

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MBM29SL800TE/BE-90/10

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(Continued)

The standard MBM29SL800TE/BE offer access times 90 ns and 100 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) ,

write enable (WE) , and output enable (OE) controls.

The device supports pin and command set compatible with JEDEC standard E2PROMs. Commands are written

to the command register using standard microprocessor write timings. Register contents serve as input to an

internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch

addresses and data needed for the programming and erase operations. Reading data out of the devices is similar

to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded

Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies

proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is

accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which

is an internal algorithm that automatically preprograms the array if it is not already programmed before executing

the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell

margin.

Each sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)

The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29SL800TE/BE are erased when shipped from the

factory.

The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low VCC detector automatically

inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,

by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been

completed, the device internally returns to the read mode.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The MBM29SL800TE/BE memories electrically erase the

entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are pro-

grammed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

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