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WS128J0PBAW11 Datasheet(PDF) 2 Page - SPANSION |
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WS128J0PBAW11 Datasheet(HTML) 2 Page - SPANSION |
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2 / 97 page  2S29WS128J/064J S29WS-J_00_A6 May 11, 2006 Dat a S h ee t General Description The S29WS128J/064J/S29WS064J is a 128/64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 8,388,608/4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0- volt VHH on ACC may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers. At 80 MHz, the device provides a burst access of 9.1 ns at 30 pF with a latency of 46 ns at 30 pF. At 66 MHz, the device provides a burst access of 11.2 ns at 30 pF with a latency of 56 ns at 30 pF. The device operates within the wireless temperature range of -25°C to +85°C, and is offered in Various FBGA packages. The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of pro- gram or erase operations. The device is divided as shown in the following table: The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output En- able (OE#) to control asynchronous read and write operations. For burst operations, the device additionally requires Ready (RDY), and Clock (CLK). This implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. The burst read mode feature gives system designers flexibility in the interface to the device. The user can preset the burst length and wrap through the same memory space, or read the flash array in continuous mode. The clock polarity feature provides system designers a choice of active clock edges, either rising or falling. The active clock edge initiates burst accesses and determines when data will be output. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. The Erase Suspend/Erase Resume feature enables the user to put erase or program on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. Program suspend is also offered. Bank Quantity Size 128Mb 64 Mb A 8 8 4 Kwords 31 15 32 Kwords B 96 48 32 Kwords C 96 48 32 Kwords D 31 15 32 Kwords 8 8 4 Kwords |
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