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56F8036 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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56F8036 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 164 page  56F8036 Data Sheet, Rev. 3 4 Freescale Semiconductor Preliminary Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56F8036 Features . . . . . . . . . . . . . . . . . . . . . 5 1.2. 56F8036 Description . . . . . . . . . . . . . . . . . . . 7 1.3. Award-Winning Developme . nt Environment 8 1.4. Architecture Block Diagram 8 1.5. Product Documentation . . . . . . . . . . . . . . . 16 1.6. Data Sheet Conventions. . . . . . . . . . . . . . . 16 Part 2: Signal/Connection Descriptions . . 17 2.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2. 56F8036 Signal Pins . . . . . . . . . . . . . . . . . 21 Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 33 3.4. Internal Clock Source . . . . . . . . . . . . . . . . . 34 3.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 34 3.6. Ceramic Resonator . . . . . . . . . . . . . . . . . . . 35 3.7. External Clock Input - Crystal Oscillator Option. . . . . . . . . . . . . . 35 3.8. Alternate External Clock Input . . . . . . . . . . . 36 Part 4: Memory Maps . . . . . . . . . . . . . . . . . 36 4.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 36 4.2. Interrupt Vector Table . . . . . . . . . . . . . . . . . 37 4.3. Program Map . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.5. EOnCE Memory Map . . . . . . . . . . . . . . . . . 41 4.6. Peripheral Memory-Mapped Registers . . . . 42 Part 5: Interrupt Controller (ITCN) . . . . . . . 56 5.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3. Functional Description . . . . . . . . . . . . . . . . . 56 5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 58 5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 59 5.6. Register Descriptions . . . . . . . . . . . . . . . . . 59 5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Part 6: System Integration Module (SIM) . . 79 6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3. Register Descriptions . . . . . . . . . . . . . . . . . 81 6.4. Clock Generation Overview . . . . . . . . . . . . 107 6.5. Power-Saving Modes . . . . . . . . . . . . . . . . 108 6.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.7. Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 112 Part 7: Security Features . . . . . . . . . . . . . 112 7.1. Operation with Security Enabled . . . . . . . 112 7.2. Flash Access Lock and Unlock Mechanisms . . . . . . . . . . 113 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . 114 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 114 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . 114 8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . 117 Part 9: Joint Test Action Group (JTAG) . . 122 9.1. 56F8036 Informatio . . . . . . . . . . . . . . . . .n 122 Part 10: Specifications . . . . . . . . . . . . . . . .122 10.1. General Characteristics . . . . . . . . . . . . . . 122 10.2. DC Electrical Characteristics . . . . . . . . . . 126 10.3. AC Electrical Characteristics . . . . . . . . . . 129 10.4. Flash Memory Characteristics . . . . . . . . . 129 10.5. External Clock Operation Timing . . . . . . . 130 10.6. Phase Locked Loop Timing . . . . . . . . . . . 131 10.7. Relaxation Oscillator Timing. . . . . . . . . . . 131 10.8. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . 133 10.9. Serial Peripheral Interface (SPI) Timing . 134 10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 137 10.11. Serial Communication Interface (SCI) Timing. . . . . . . . . . . . . . . . . 138 10.12. Freescale’s Scalable Controller Area Network (MSCAN) Timing . . 139 10.13. Inter-Integrated Circuit Interface (I2C) Timing . . . . . . . . . . . . . . . . 139 10.14. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 141 10.15. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . 142 10.16. Equivalent Circuit for ADC Inputs . . . . . . 143 10.17. Comparator (CMP) Parameters . . . . . . . 143 10.18. Digital-to-Analog Converter (DAC) Parameters . . . . . . . . . . . 144 10.19. Power Consumption . . . . . . . . . . . . . . . 145 Part 11: Packaging . . . . . . . . . . . . . . . . . . .147 11.1. 56F8036 Package and Pin-Out Information . . . . . . . . . . . 147 Part 12: Design Considerations . . . . . . . . 150 12.1. Thermal Design Considerations . . . . . . . . 150 12.2. Electrical Design Considerations . . . . . . . 151 Part 13: Ordering Information . . . . . . . . . . 152 Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 153 56F8036 Data Sheet Table of Contents |
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